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Questions tagged [intel-fpga]

Intel FPGA - formally known as Altera - which is wholly owned subsidiary of Intel, is a major brand of Field Programmable Gate Arrays (FPGA).

Intel FPGA is a company part of Intel creating FPGAs and CPLD. It is a Xilinx competitor. Famous associated name are:

  • Stratix
  • Cyclone
  • Arria
  • MAX

It also offers intellectual properties like Nios II Processor, Hardware development programs like Quartus, software development programs like Nios Embedded Software.

This link points to various trainings that are free and offered by Intel FPGA.

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How do I generate N counters inside a generate block to load test an FPGA?

I need to estimate the maximum number of 16-bit counters that a FPGA board can fit. I created a 16-bit counter module with enable (en) and terminal count (TC), and instantiated this inside a generate block in a top level module. However, I need to…
pranav bharadwaj
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Quartus 20.1 high logic cell usage

I stumbled across a really weird behavior in Quartus Lite Edition. I'm setting up a development container for a university project using the DE2-115 Board with a Cyclone IV FPGA. Using Quartus 19.1 everything builds well and works as expected but if…
Lehrlii
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FPGA multiple firmwares on one serial flash memory (intel/altera)

Preloaded more than one firmware to flash memory. Can I make the FPGA reboot during its operation and start loading its firmware not from the beginning of the flash drive, but from a different memory area? This loads a different firmware preset.
Amelkai
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Does Quartus support in-memory synthesis?

I'm working on a project that generates a large number of components. I'm having the problem that Quartus is generating an extremely large number of files in the /db directory, on the order of hundreds of thousands. The system I am working on has…
Heiko
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Problem with using division operator in Quartus using VHDL

We need to divide two integers using VHDL and run on FPGA. Below is the the code we wrote for integer addition and it compile in the Quartus but when we try to compile the division code it gave error as "Error (10327): VHDL error at…
Dilum Bandara Wijesundara
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Connecting Waveshare High-Precision AD/DA Board (ADS1256) to DE10-Nano Kit

I'm currently working on an ECG project and I'm having some difficulties using the Waveshare High-Precision AD/DA Board (which has an ADS1256 ADC and is meant for use with RPI) with the Terasic DE10-Nano Kit. I'm using an Altera SPI Master…
fin121
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What am I doing wrong? Testbench not updating correctly

I am trying to implement the testbench so that after 3 ticks, each input gets the new specified valued. For example, first 3 seconds (or ticks) A = 10, B = 0, and then the next 3 seconds (3 seconds to 6 seconds) A = 10, B = 16 and etc. However, on…
RhinoECE
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How to implement nand2tetris processor on a real FPGA?

I followed the nand2tetris course (https://www.nand2tetris.org/course) with the main intent to learn how to build a soft processor on a real FPGA. While the course was simple enough, now that I am starting with the FPGA implementation I feel a bit…
Giuseppe Rossini
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64-bit ALU outputs are showing high impedance on TestBench waves

I have to make a 64 Bit ALU that takes in A and B 64-bit inputs, a carry_in input and outputs a 64bit result along with a 1-bit carry_out. There is also a 5 bit function-select FS. Where FS[0] controls whether B is inverted or not (using a 2to1…
RhinoECE
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Behavioral module for Adder that adds two 64-bit inputs and carry in Input. How to assign carry-out to MSB of the sum?

My desired functionality will be to add A, B, and cin (where A and B are 64 bits, and cin is one bit). So the actual sum (the actual result) can either be 64 bits or even 65 bits, right? So I want the output "sum" to be 64 bits, and then the…
RhinoECE
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Debugging why SPI Master is Reading Arbitary Values

I have an SPI bus between a MAX V device and an AM335x processor. The MAX V device has an SPI setup to repeatedly send a STD_LOGIC_VECTOR defined as "x0100". This seems to work fine. The output on a scope is repeatedly the same value. In Linux, I…
Ollie Sharratt
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Best Way to declare a LUT in OpenCL (Intel FPGA)

I need to declare three LUT's in an OpenCL kernel, so: What is the optimal way to declare a LUT in Intel OpenCL FPGA? I have saw examples about this, but in the examples they used a switch/case structure. I think the best way is declare an array for…
Diego Ruiz
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User Flash Memory Page Address

I'm using max10 FPGA user flash memory in my project . It has 4 pages in one sector each page is 64kbits of size. Now how to identify what is starting and ending address of each page in memory to write or read data from flash memory.
manu
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NIOS II IDE unsuably slow

I've installed Quartus and NIOS II IDE on my Linux machine. Originally I tried importing an existing NIOS II Project into Eclipse, but it just sits there spinning away and eventually tells me it can't import the project because it already exists. I…
DiBosco
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A low logic level turn on LEDs and high logic level turn off LEDs in quartus with Altera Cyclone FPGA

I have a development board with an EP4CE6E22C8 FPGA. And I have the following verilog code in Quartus Prime: module Test(out); output [7:0] out; assign out = 8'b00111100; endmodule The pin planner has been configured as pointed by the schematic.…
RdlP
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