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We need to divide two integers using VHDL and run on FPGA. Below is the the code we wrote for integer addition and it compile in the Quartus but when we try to compile the division code it gave error as

"Error (10327): VHDL error at divider.vhd(25): can't determine definition of operator ""/"" -- found 0 possible definitions".

when we search through the internet we show there are many posts that says generally integer division in VHDL not carrying out. Can anybody give us some advise to solve this problem. Thanks in advance

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity divider is

port 
    (
    --clock, resetn :IN STD_LOGIC;
       
        a       : in  std_logic_vector (11 downto -4);
        b      : in  std_logic_vector (11 downto -4);
        Enable_FA: in std_logic;
        result  : out  std_logic_vector (23 downto -8)
    );

end entity;

architecture behaviour of divider is
begin
process(a,b,Enable_FA)
    begin
    if (Enable_FA='1') then
        result <= a / b;
    end if; 
end process;    
end behaviour;
Dilum Bandara Wijesundara
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  • Division isn't defined in Synopsys package std_logic_unsigned (nor in Synopsys package std_logic_arith). std_logic_vector has a n index type of natural, it can't have negative index values. You're not attempting integer division, integer is a scalar type. –  Apr 07 '21 at 06:59
  • Does this answer your question? [can't determine definition of operator ""/"" -- found 0 possible definitions](https://stackoverflow.com/questions/51105253/cant-determine-definition-of-operator-found-0-possible-definitions) –  Apr 07 '21 at 07:37
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    @MatthewTaylor `std_logic_unsigned` and `numeric_std` are compatible in so far as there are no type or function overlaps. The common clash comes from `std_logic_arith` and `numeric_std` where both packages define `signed` and `unsigned` types. – Tricky Apr 07 '21 at 15:41
  • Thank you @Tricky. I think I was confusing my `std_logic_unsigned` and my `std_logic_arith`. – Matthew Taylor Apr 07 '21 at 16:01
  • [IEEE Std 1076-2008 12.4, Use clauses, para 8](https://i.stack.imgur.com/ySDR9.jpg). E.g. with use clauses for numeric_std and std_logic_arith the type declaration for unsigned from either would not be directly visible. Using a type unsigned declaration from numeric_std on a port or parameter and associating it with an actual using a type unsigned declaration from unmodified package std_logic_arith would result in error. –  Apr 07 '21 at 20:10
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    FPGAs typically don't have dedicated hardware for computing division, so you have to build a divider from other parts (like multipliers and RAMs). That means it's usually not a one-liner in VHDL, but rather you need to instantiate a block that implements a division algorithm. I think all the major FPGA vendors provide free IP cores for computing divisions (but you may prefer to write your own). – Harry Apr 07 '21 at 22:43
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    Try to stick with numeric_std and look for divider cores in the IP catalogue of whatever program you are using, most likely it is Quartus Prime – quantum231 Apr 08 '21 at 07:03

0 Answers0