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I'm currently working on an ECG project and I'm having some difficulties using the Waveshare High-Precision AD/DA Board (which has an ADS1256 ADC and is meant for use with RPI) with the Terasic DE10-Nano Kit.

I'm using an Altera SPI Master peripheral in Qsys with the following settings:

  • SCLK rate: 20000
  • Data Width: 8 bits
  • Shift Direction: MSB first
  • Clock Polarity: 0
  • Clock Phase: 1
  • No synchronizer stages

For the remaining required signals I'm using Avalon PIO:

  • DRDY (Input)
  • RST (output)
  • PWR (output)

Additionally, there's a Nios2 CPU which makes use of alt_avalon_spi_command to send SPI commands and IOWR_ALTERA_AVALON_PIO_DATA to control the PIO.

The issue I'm experiencing, is that the DRDY signal is never asserted (it's expected to go LOW before being able to read data). I understand this signal should be used with a pull-up resistor; I've tried the following, neither of which worked:

  1. Configure internal pull up on DE10-Nano GPIO pin
  2. Use external pull up resistors (10K/56K)

I understand I should be able to read the Chip ID of the ADS1256, prior to configuring it. I first reset the device, as per: https://github.com/waveshare/High-Precision-AD-DA-Board/blob/master/Jetson%20nano/ADS1256/C/obj/ADS1256.c#L39

    /* RESET */
    IOWR_ALTERA_AVALON_PIO_DATA( WAVESHARE_ADS_RST_BASE, HIGH );
    usleep(200);
    IOWR_ALTERA_AVALON_PIO_DATA( WAVESHARE_ADS_RST_BASE, LOW );
    usleep(200);
    IOWR_ALTERA_AVALON_PIO_DATA( WAVESHARE_ADS_RST_BASE, HIGH );

Then I wait for DRDY to go LOW and this never seems to happen, regardless of the above-mentioned setup for the pull up resistor:

alt_u8 ADS1256_wait_DRDY( void ) {
    for( int i=0; i<50; i++ ) {
        alt_u8 drdy = ADS1256_DRDY_get_level();
        if ( drdy == LOW ) {
            printf( "DRDY asserted\n" );
            return 0;
        } else {
            usleep( DELAY_DRDY );
        }
    }
    printf( "Timeout: DRDY not asserted.\n" );
    return -1;
}

I'm probing using a Hobby Components Logic Analyser. The pin connections are elaborated below:

AD/DA        RPI PIN       DE10-Nano   Location    Standard    HDL Signal        Direction  Logic Analyzer
==========================================================================================================
3v3          3v3           3v3                                                                  
GND          GND           GND                                                                             
MOSI         19 (GPIO 10)  GPIO_0(0)   PIN_V12     3.3V LVTTL  SPI_MOSI          OUT        D0                  
MISO         21 (GPIO 9)   GPIO_0(2)   PIN_W12     3.3V LVTTL  SPI_MISO          IN         D1 
SCK          23 (GPIO 11)  GPIO_0(4)   PIN_D8      3.3V LVTTL  SPI_SCK           OUT        D2 
P3 (CS_PIN)  15 (GPIO 22)  GPIO_0(1)   PIN_E8      3.3V LVTTL  SPI_SS_n(0)*      OUT        D3 
P1 (RST)     12 (GPIO 18)  GPIO_0(3)   PIN_D11     3.3V LVTTL  ADS_RST           OUT        D4  
P0 (DRDY)    11 (GPIO 17)  GPIO_0(6)   PIN_AE15    3.3V LVTTL  WAVESHARE_DRDY    IN         D5

The logic analyser output is as following: PulseView

Any help on how to set this up is much appreciated. Apologies if my post is not great, I'm fairly new to posting on these forums.

fin121
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1 Answers1

1

Some of the pin assignments were not correct. After fixing these and testing with a different microcontroller instead of the AD/DA board, the DRDY is asserted, but the issue persists with the waveshare board. It looks like a board specific issues, so I've contacted the manufacturer for assistance.

fin121
  • 21
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