Stack Overflow
Stack Overflow

Questions tagged [intel-fpga]

Intel FPGA - formally known as Altera - which is wholly owned subsidiary of Intel, is a major brand of Field Programmable Gate Arrays (FPGA).

Intel FPGA is a company part of Intel creating FPGAs and CPLD. It is a Xilinx competitor. Famous associated name are:

  • Stratix
  • Cyclone
  • Arria
  • MAX

It also offers intellectual properties like Nios II Processor, Hardware development programs like Quartus, software development programs like Nios Embedded Software.

This link points to various trainings that are free and offered by Intel FPGA.

492 questions
0
votes
1 answer

How to create wave forms in ModelSim Altera Starter

I'm using Altera ModelSim 10.1d for a verilog project for a class. I can't figure out how to run the simulation properly. I have a very simple verilog file (just a 2 to 1 multiplexer) and I want to try 4 different combinations of inputs. According…
Steel Nation
  • 510
  • 8
  • 26
0
votes
2 answers

compiler errors when compiling *.vhdl into a library - Altera Quartus II

I've downloaded the floating point package from http://www.vhdl.org/fphdl/ and did the following: I included the math_utility_pkg.vhd, fixed_pkg_c.vhd and float_pkg_c.vhd files in my project I assigned them to a library (following the instructions…
user3209815
  • 357
  • 1
  • 11
  • 25
0
votes
1 answer

VHDL RAM 256x8 bit

I need to write the VHDL-code for a 256x8 bit RAM. I will use bidirectional buses to manage reading and writing, but I figured I could do that using a schematic file. What I need is to create the RAM-memory as a component, but I'm struggling…
user3398479
  • 1
  • 1
0
votes
1 answer

Behavioral to Structural Conversion Problems VHDL

I designed a primality testing for Rabin Miller algorithm in behavioral type. I used functions to create my modules. Unfortunately, when I tried to synthesize it by my Altera Kit via Quartus, I realized that function are not synthesize. Here I will…
user3300910
  • 19
  • 1
  • 2
  • 6
0
votes
1 answer

Calling a Component Inside Another Component "Port Mapping" (Illegal Statement) VHDL

I am facing a confusing problem in my program. I need in my program to port map (calling) a component. Also, inside the component, I need to do another port mapping (calling) which is illegal in VHDL. Do you have an alternative solution to this…
user3300910
  • 19
  • 1
  • 2
  • 6
0
votes
1 answer

Why can't make work my VHDL program using elsif not recognize one state

I'am a spanish user an newbie on VHDL programming the problems its that I was trying to make a machine state with the CASE but don't work. then i decide to do with ELSIF instruction all its working perfect but the state 0010 its not working a I…
Miguelon
  • 3
  • 2
0
votes
1 answer

How to generate delay in verilog using Counter for Synthesis and call inside Always block?

I want to generate delay using counter, actually here I use counter to generate delay after each 1 Bit transfer, so that its better understand externally on fpga pin from which by SPI(serial) LCD is connected with it. Therefore I had created a shift…
Shrikant Vaishnav
  • 80
  • 1
  • 5
  • 13
0
votes
1 answer

Simulation of VHDL file on Quartus 13

Over past days the option "Run Functional Simulation" (in waveform part) in Altera Quartus 13 here (i use in Ubuntu 11.10) was working fine, but since yesterday It, all of sudden, is not working. When I click in the option, it's opened a tiny grey…
Inácio Medeiros
  • 85
  • 2
  • 9
0
votes
2 answers

Verilog Register to output

I am working with an Altera DE2 development board and I want to read an input in on the switches. This is stored in registers. Based on a counter these registers are incremented. The registers are then supposed to be output to the Seven Segment…
Michael Miner
  • 964
  • 2
  • 17
  • 39
0
votes
1 answer

counter program (assembly machine code) for MIPS processor using quartus 2

I have written a machine level code for a counter that should increment to 15 and then decrement to 10, once 15 is reached, and then reset to 0, once 10 is reached. I have written this program in .mif files. I have used 2 .mif files, one for…
bobdxcool
  • 91
  • 1
  • 1
  • 10
0
votes
0 answers

Update .mif file using In System memory content editor is showing no instances

I am using DE1 and VHDL. I want to update my mif file constantly and display it on VGA. I used one of the tutorials online to use In System memory content editor. But, once I complete the process, I see no instance is being created in spite of…
San
  • 151
  • 5
  • 15
0
votes
2 answers

How to place component parts on RAM on chip

I am making some kind of cache and i am using some tables (big ones) inside entity which are composed of std_logic_vectors and i am doing it in Quartus 2 web edition. Everything works fine in simulation, but when i try to synthesize it its being…
Dejan
  • 3,046
  • 3
  • 28
  • 43
0
votes
2 answers

Why does compiling C take so long time?

When I compile a C project it can take about 90 seconds even though I use a fast Intel I7 CPU. Is it because compilation is a low-level task or why are my build times so long? My environment is the Nios 2 IDE for Altera DE2 FPGA.
Niklas Rosencrantz
  • 25,640
  • 75
  • 229
  • 424
0
votes
0 answers

IEEE Float input to BCD convertion

If i use one std_logic_vector (31 downto 0) as input of my entity. Exists any form of using this 32 bits (IEEE Format) to convert them to ASCII form ? I have 3.14: input ----> 0100 0000 0100 1000 1111 0101 1100 0011 (in IEEE 32 bits form) output…
Antônio Vieira
  • 9
  • 1
  • 6
0
votes
2 answers

convert a std_logic_vector INPUT to IEEE Float type

How convert a std_logic_vector INPUT of the my entity in a IEEE Float type, to do some operations in my process? My entity need receive a IEEE Float of A/D converter.
Antônio Vieira
  • 9
  • 1
  • 6
1 2 3
…
32 33