Stack Overflow
Stack Overflow

Questions tagged [intel-fpga]

Intel FPGA - formally known as Altera - which is wholly owned subsidiary of Intel, is a major brand of Field Programmable Gate Arrays (FPGA).

Intel FPGA is a company part of Intel creating FPGAs and CPLD. It is a Xilinx competitor. Famous associated name are:

  • Stratix
  • Cyclone
  • Arria
  • MAX

It also offers intellectual properties like Nios II Processor, Hardware development programs like Quartus, software development programs like Nios Embedded Software.

This link points to various trainings that are free and offered by Intel FPGA.

492 questions
0
votes
1 answer

Why does combining these if statements result in higher logic element utilization?

I have a project in verilog where I'm keeping track of the date. I have the following code to handle the different length of months, unless I am mistaken I can combine these all by oring each condition and just having one if statement. This however…
Ben Pye
  • 807
  • 7
  • 14
0
votes
1 answer

Quartus 13.1 installer giving segmentation fault (core dumped)

I'm trying to install Quartus 13.1 on my Xubuntu 14.04 64-bit edition. The downloaded file is a .run installer, which I make executable by executing: sudo chmod +x installer.run ./installer Which gives a segmentation fault (core dumped)…
user2742907
  • 87
  • 1
  • 11
0
votes
1 answer

Increment and Decrement using verilog codes in quartus

My project is to design a verilog code that gives an output on the 7segments (HEX0,HEX1,HEX2,HEX3) and output must increase when the button KEY0 is pressed on the board 1 by 1, and decrease when the button KEY1 is pressed using Altera Board (Cyclone…
Ebubekir Büyüktosun
  • 3
  • 1
  • 2
0
votes
1 answer

Is there anyway to read the board serial number from a altera Cyclone V FPGA?

Is there anyway to read the board serial number from a Cyclone V FPGA?
Marador
  • 11
0
votes
1 answer

ADC converter does not display right value on 7 segment FPGA

Im writing a VHDL code that allows connect ADC7475 (12 bit with 4 leading zeros(total 16 bit)) to FPGA board. My target is displaying the digital output value of ADC on 7 segment when provide analog signal (Vin pin of ADC). Here is my…
lft
  • 113
  • 1
  • 1
  • 12
0
votes
1 answer

Error (10822): couldn't implement registers for assignments on this clock edge

I cant find what i'm doing wrong, i would be glad if someone could help me on this... entity fsmF is port(S, R : in std_logic; Q : out std_logic); end; architecture FSM_beh of fsmF is begin process(S, R) begin if S = '0' then …
SDkkk
  • 1
  • 1
  • 1
0
votes
2 answers

VHDL Need pin to stay high for (exactly) one second, then switch to low automatically. triggered manually ( not syncronized )

So...i need an output pin to stay high for a second and switch back to low. It is triggered manually by a user pressing a button, changing state in a FSM with a much higher speeded clock. entity red_green is port( clk : in …
user1994679
  • 1
  • 2
0
votes
1 answer

How to see samba shares when running a Nios II shell as administrator under Windows 7

I'm running into some problems with some Nios II code I'm trying to run using Quartus Web Edition 13.1 running under Windows 7. One of the problems I'm seeing is that if I launch the Nios II shell as an administrator and then run the "df" command, I…
Ciano
  • 554
  • 5
  • 16
0
votes
2 answers

VHDL testbench for Modelsim (Altera)

I'm in the process of writing the VHDL code for Salsa20 stream cipher. Its main function is the 'quarterround' which I have successfully written. I want to test it in Modelsim before moving on but I am encountering difficulties. I understand I have…
Chaz Tortoise
  • 5
  • 6
0
votes
1 answer

How to add the value of an std_logic_vector to an index in VHDL?

I'm writing a flexible MUX, it has a generic which determines the number of selection lines but also the number of inputs and outputs to the system. If, for example, size = 3; The system will have 8 inputs, 64 outputs and 3 selection lines. This…
user34920
  • 227
  • 3
  • 6
  • 12
0
votes
3 answers

Inferred RAM doesn't initialize in ModelSim Altera edition

I have a memory module for an Altera FPGA target that I've written to be inferred into one of Altera's ALTSYNCRAM blocks. The memory is 1024x16 and I have a memory initialization file specified with an attribute. When synthesizing, the synthesis…
QuantumRipple
  • 1,161
  • 13
  • 20
0
votes
1 answer

does Altera stratix III or Stratix II devices support partial reconfiguraion

I need to inquire this question that stratix II or III devices do not support partial reconfiguration? Does anyone has experience of working over Xtremedata XD1000 or XtremeData XD2000i devices which has Stratix II and III respectively as…
SJa
  • 487
  • 4
  • 14
0
votes
2 answers

Symmetric Cipher HDL

Suppose an okay C programmer wanted to write VHDL code of a given symmetric cipher from scratch..anyone have any ideas or tips on an not overly difficult one to write? It's just for proof of concept for a final year project. I have got AES working…
Chaz Tortoise
  • 5
  • 6
0
votes
1 answer

VHDL clock divider works on board but fails in simulation

I'm presently trying to use VHDL to design a traffic light controller, which I'm programming on an Altera EPM240T100C5 with a custom expansion board for displaying the traffic lights. As the slowest clock setting on the board is still faster than I…
The General
  • 1,239
  • 2
  • 17
  • 28
0
votes
1 answer

VHDL timer that returns 1 when it has reached its count

I'm trying to design a traffic light controller and for this I need a number of different timers. Thus, I designed this generic timer in VHDL: library IEEE; use IEEE.std_logic_1164.all, IEEE.numeric_std.all; entity timer is generic (n: NATURAL…
The General
  • 1,239
  • 2
  • 17
  • 28
1 2 3
…
32 33