How to place component parts on RAM on chip

Question

I am making some kind of cache and i am using some tables (big ones) inside entity which are composed of std_logic_vectors and i am doing it in Quartus 2 web edition.

Everything works fine in simulation, but when i try to synthesize it its being done ONLY with latches, AND and OR components.

Is there any way to specify Quartus to use memory modules for those tables instead of these combination elements? Or maybe something can be done from VHDL code itself.

library ieee;
use ieee.std_logic_1164.all;

package UTIL_PACK is
    type matrix16x8 is array (0 to 15) of std_logic_vector(0 to 7);
    type matrix2p4x8 is array (0 to 2**4) of matrix16x8;
end package;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.util_pack.all;

entity  RAM16B is

    port(
        signal RD: in std_logic;
        signal WR: in std_logic;
        signal CLK: in std_logic;
        signal A: in std_logic_vector(7 downto 0);
        signal D: inout matrix16x8;
        signal FC: out std_logic 
    );

end entity ;

architecture RAM16B_IMPL of RAM16B is
    signal memory: matrix2p4x8 := ((others => (others => (others => 'Z')))); 
begin 

run:process(clk)is
    variable slot:integer range 0 to 15 :=0;
    begin
        if(clk='1') then
            slot := TO_INTEGER(unsigned(A)) rem 16;
            if(rd = '1')then
                FC<='0';
                for i in 0 to 3 loop
                    D(i) <= memory(i)(slot);
                end loop;
                FC<='1';
            elsif(wr = '1')then
                FC<='0';
                for i in 0 to 3 loop
                    memory(i)(slot) <= D(i);
                end loop;
                FC<='1';
            else 
                FC <= 'Z';
                D <= ( others => ( others => 'Z' ));
            end if;
        else
            FC <= 'Z';
            D <= ( others => ( others => 'Z' ));
        end if;
    end process;

end architecture RAM16B_IMPL;

RAM consists of 16 blocks of memory, each block is 16 bytes. I am trying to read more data parallely so I am reading/writing 16 bytes of data per cycle. Slot defines block in which reading/writing is being done.

Answer 1

Yes, you can do it from your VHDL code. To make sure that Quartus understands that you are modeling a memory, you should code it as described in Altera's Recommended HDL Coding Styles guide. Take a look at the section called Inferring Memory Functions from HDL Code (http://www.altera.com/literature/hb/qts/qts_qii51007.pdf), then modify your code accordingly.

It is probably a good idea to start with the exact memory model suggested by Altera, and making sure that Quartus synthesizes the design using the FPGA's dedicated memory bits. Next, you can gradually change your model to implement the desired behavior, always synthesizing and looking at the compilation reports to make sure your changes didn't deviate from what Quartus infers as a memory block.

Answer 2

If you really want to make sure you use the hard memory blocks, you should either use the mega-function wizard to craft a custom ram component, or directly instantiate an altsyncram component from the library and use the generics to configure it how you want (this can be tricky if you're not extremely familiar with the options). This causes porting issues, but any time you infer ram you generally have porting issues anyway. Using a custom library component just makes it very obvious and easy to identify where you might have problems if you ever do need to migrate to something else.

As for your specific implementation, there's no way you're going to get latches automatically migrated into the hard ram blocks which are edge driven devices. Use rising_edge(clk) instead of clk='1' in your process to fix this.

Also, there is no support for tri-state operation internal to the chip, you need independent data in and data out ports. You are getting lots of discrete logic because and & or gates are being used to emulate a tri-state bus (and because of the latch issue, above).