Why can't make work my VHDL program using elsif not recognize one state

Question

I'am a spanish user an newbie on VHDL programming the problems its that I was trying to make a machine state with the CASE but don't work. then i decide to do with ELSIF instruction all its working perfect but the state 0010 its not working a I don't know why its a very ease program but don't understand why y is not working EXCUSE MY POOR ENGLISH but I do my best thanks I show the program next:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

--definimos identidad de la interfaz
entity interfaz is 
port(
    sen:in std_logic_vector(3 downto 0);--entrada de sensor bus de 4 bits
    clk:in std_logic;
    mda, mdr, mia, mir:out std_logic);--mdr,mda=motor derecho retroceso,avance == mia,mir=motor izquiero avance,retroceso
end interfaz;
--comenzando arquitectura de interfaz
architecture behavior of interfaz is
----------------------------------------------------
--Instruccion con herramienta elseif
process
begin
wait until clk'event and clk='1';
if (sen=(0000)) then --alto
mda<='0'; 
mdr<='0'; 
mia<='0'; 
mir<='0';
elsif (sen=(0001)) then --retroceso
mda<='0';
mdr<='1';
mia<='0';
mir<='1';
elsif (sen=0010) then --avance
mda<='1';
mdr<='0';
mia<='1';
mir<='0';
elsif (sen=(0100)) then --izquierda
mda<='0';
mdr<='1';
mia<='1';
mir<='0';
elsif (sen=(1000)) then --derecha
mda<='1';
mdr<='0';
mia<='0';
mir<='1';
end if;

end process;
end behavior;

Answer 1

The sen=0010 appears like sen is compared to a 4-bit vector, but it is actually compare with the decimal value 0010 = 10 = ten, due to the lack of "" around the 0010 value. Fix this in all place with by adding "", like "0010".

VHDL is basically strong typed, but the use ieee.std_logic_unsigned.all; adds functions that allows compare between std_logic_vector and integer, and for this reason the problem passes syntax check.

Also:

• Fix a syntax error by adding begin before the process, since that is required in architecture
• Consider using if rising_edge(clk) instead of wait until clk'event and clk='1'
• Consider rewrite with case