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How convert a std_logic_vector INPUT of the my entity in a IEEE Float type, to do some operations in my process? My entity need receive a IEEE Float of A/D converter.

Antônio Vieira
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2 Answers2

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VHDL doesn't have a float type by default - it has real which is not synthesisable.

However, the IEEE-standardised VHDL floating-point types are perfectly synthesisable.

You'll have to cast your std_logic_vector as an unsigned or signed vector first and then convert to a suitable floating-point type, which need not be an IEEE-754 defined type

Martin Thompson
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  • how my std_logic_vector is converted ? if i try to_integer(to_float(signed(my_std_logic_vector))) i get a error. i need get the integer value of my float number in my_std_logic_vector. – Antônio Vieira Oct 07 '13 at 14:29
  • Error (10779): VHDL error at float_pkg_c.vhdl(4314): expression is not constant Error (10657): VHDL Subprogram error at float_pkg_c.vhdl(4314): failed to elaborate call to subprogram "TO_INTEGER" Error (10657): VHDL Subprogram error at teste.vhd(28): failed to elaborate call to subprogram "to_integer" – Antônio Vieira Oct 07 '13 at 14:40
  • @AntônioVieira What format is `my_std_logic_vector` in? You should only cast it to signed if it is indeed signed - in the statement you're using, the to_float is pretty much meaningless. – zennehoy Oct 07 '13 at 15:01
  • Hi @zennehoy. `my_std_logic_vector` is a `in std_logic_vector(32 downto 1);` – Antônio Vieira Oct 07 '13 at 15:51
  • I want get all the digits of the float number. Because this i want get the integer part of them. – Antônio Vieira Oct 07 '13 at 16:12
  • after i declare a variable `variable input_signed : signed (32 downto 1);` where i put the my_std_logic_vector `input_signed := signed(my_std_logic_vector);` – Antônio Vieira Oct 07 '13 at 16:17
  • after this i do: `my_float := float32(input_signed);` `my_integer := to_integer(my_float); <- i get error here.` Error (10779): VHDL error at float_pkg_c.vhdl(4314): expression is not constant Error (10657): VHDL Subprogram error at float_pkg_c.vhdl(4314): failed to elaborate call to subprogram "TO_INTEGER" Error (10657): VHDL Subprogram error at teste.vhd(28): failed to elaborate call to subprogram "to_integer" – Antônio Vieira Oct 07 '13 at 16:20
  • @AntônioVieira Are you trying to round the floating point number to the nearest integer, or convert the bit pattern representing the float into an integer? – Martin Thompson Oct 07 '13 at 16:24
  • i don't need round the number. In 3.742 i want get 3. In 5.78 i want get 5. in 456.17 i want get 456. – Antônio Vieira Oct 07 '13 at 22:04
  • to do this i need execute to_integer function. But i get a error above – Antônio Vieira Oct 07 '13 at 22:05
  • What compiler are you using? Can you update your question with a complete, minimal, compilable testcase so we can see exactly what you're talking about. working through it in comments isn't going to work I don't think... – Martin Thompson Oct 08 '13 at 09:22
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VHDL's floating point type (real) is not synthesizable (except perhaps by some very specialized tools), so if you have an input std_logic_vector in IEEE float form you will have to extract and process the required data fields (sign, exponent, mantissa) yourself (or use a library that does it for you, knowing the large amount of hardware resources this will consume).

Personally, I would avoid using floating point if at all possible, and stick to using fixed point instead.

zennehoy
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  • This is untrue, please see Martin's answer. – Josh Oct 07 '13 at 13:29
  • @Josh Sorry, I so rarely use floating point in VHDL that I forgot the type is called `real` rather than float. I still stand by my point though that using floating point in hardware should be avoided, since it is difficult to synthesize, tends to require vast amounts of resources, and can be replaced by fixed point for almost all sensical implementations of a given hardware algorithm. – zennehoy Oct 07 '13 at 15:07
  • Agreed that it should be avoided as possible. – Josh Oct 07 '13 at 15:27