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Is there an example (VHDL) available how to setup the CSR interface for the Altera Max10 ADC converter? The Altera manual gives only limited information and only following description:

enter image description here

It would be a big help to see the relevant interface in a timing diagram.

Thanks in advance!

Norick
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    [Avalon Interface Specifications](https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/mnl_avalon_spec.pdf), [Avalon MM Master VHDL Templates](http://www.alteraforum.com/forum/showthread.php?t=19053) and [Avalon Memory-Mapped Master Templates](https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-mm.html). Also see [Completing ADC Design](https://documentation.altera.com/#/00003728-AA$AA00049837) (Amazing what a little googling will uncover). –  Feb 15 '16 at 07:43
  • Thanks for the input – Norick Feb 16 '16 at 09:43
  • Either answer your question yourself or consider deleting it - [questions asking us to recommend or find a book, tool, software library, tutorial or other off-site resource are off-topic for Stack Overflow](http://stackoverflow.com/help/on-topic). Answering the question might require it be reformatted to be on-topic, it's new subject matter and might eventually be worth a new tag. –  Feb 16 '16 at 10:20

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