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I want to transfer a fork-join problem in fpga. Fork-join in the sense that there will be many small components (> 100) accessing a memory component, processing input data (a few 32-bit vectors) for small amount of cycles (~50) without interactions among them and then returning the data for accessing another memory. Does this sound a case where ,in terms of interconnections, i should use a traditional bus solution or i should shift to those NoC-based structures that are offered in system level tools (Qsys altera)?

user2609910
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  • You need to clarify the question. Right now it seems that your processing components work sequential on different pieces of data. If this is the case you don't need 100 component, you need only one which will save its results to memory and start over next block of input data. – ya_urock May 17 '16 at 05:36
  • The processing components have to share a memory but process different data from that. The processing has to be accelerated so the fastest they get the data the better so they can start working. I am just wondering which bus structure would be appropriate a high speed pipelined or a NoC based... – user2609910 May 17 '16 at 08:34

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Bus connection based on star topology will cause routing problems in this case when number of endpoints is big. If data can be processed sequential then I could recommend to build custom packet based sequential network.

Processing elements (PE) can be connected in pipeline, with data traffic passing through all of PEs in streaming fashion. Then each PE will save and process only its portion from data stream and pass other data to next PE.

ya_urock
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