Hey guys so I'm very new to Verilog and Fpga's so sorry if I am missing something very simple. I am trying to interface an external SRAM that I would like to test for functionality. I have written this code along with a test bench to verify it. I will be trying to just simply write and read some data to make sure the device works properly. Since I will be trying to test this on a breadboard I am first attempting to lower the clk frequency at which my program will be running down from the sys clock of 100 MHz to 12 MHz using the clocking wizard IP in Vivado. The problem seems to be that my output from the clocking wizard is not working properly and will only output a single pulse at the incorrect frequency.
top.v:
`timescale 1ns / 1ps
module TOP(
input clk,
input btn,
output reg[7:0] io,
output WE,
output OE,
output CE_0,
output CE_1
);
clk_wiz_0 clktwelve
(
// Clock out ports
.clk_out1(clk0), // output clk_out1
// Status and control signals
.clk_in1(clk) // input clk_in1
);
wire clk1 = clk0;
reg output_enable;
reg write_enable;
reg chip_enable_low;
reg chip_enable_high;
reg[7:0] cnt=8'd0;
always @ (posedge clk1 )
if (btn==1)
begin
output_enable = 1'b0;
write_enable = 1'b1;
chip_enable_low = 1'b1;
chip_enable_high = 1'b0;
io[0] = 1'bz;
io[1] = 1'bz;
io[2] = 1'bz;
io[3] = 1'bz;
io[4] = 1'bz;
io[5] = 1'bz;
io[6] = 1'bz;
io[7] = 1'bz;
end
else begin
output_enable =1'b0;
write_enable = 1'b0;
chip_enable_high = 1'b1;
chip_enable_low = 1'b0;
if(cnt<255) cnt=cnt+1'b1;
else cnt=8'd0;
io=cnt;
end
assign OE = output_enable ;
assign WE = write_enable ;
assign CE_0 = chip_enable_low;
assign CE_1 = chip_enable_high;
endmodule
TESTBENCH:
`timescale 1ns / 1ps
module TOP_TB();
reg clk;
reg btn;
wire [7:0] io;
wire WE;
wire OE;
wire CE_0;
wire CE_1;
TOP testbench1 (
.clk(clk),
.btn(btn),
.io(io),
.WE(WE),
.OE(OE),
.CE_0(CE_0),
.CE_1(CE_1)
);
initial begin
btn = 1;
clk = 0;
#200 btn = 0;
#500000 $finish;
end
always #10 clk = ~clk;
endmodule
I plan to ultimately design a pcb board and test the asynchronous sram at maximum frequency of 100MHZ, any advice is helpful!
btw I am using a ARTY A7 35T
I tried this simple code to trouble shoot the problem and still can not get a clean response.
`timescale 1ns / 1ps
module top(
input clk,
output clk0
);
clk_wiz_0 instance1
(
// Clock out ports
.clk_out1(clk0), // output clk_out1
// Clock in ports
.clk_in1(clk) // input clk_in1
);
endmodule
and testbench:
`timescale 1ns / 1ps
module TB(
);
reg clk;
wire clk0;
top instance1 (
.clk(clk),
.clk0(clk0)
);
initial begin
clk = 0;
end
always #10 clk = ~clk;
endmodule
result:
