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I'm working on an FSM for a quadrature encoder counter, to be used on the Arty A7 35 --- this is my first VHDL project, so I apologize if I am missing something very basic. I have an internal count signal that I decrement or increment in the FSM, but when I try to assign that signal via COUNT_OUT <= count, COUNT_OUT stays at zero, even though I have been able to observe the state changing. I do this assignment at the very end of the FSM process.

simulation outputs

Further, I am not able to observe "state", "next state", or "count" in simulation --- I would appreciate help on this as well as would be very useful. These signals do not show up in the "objects" window beside the scope either

My entity declaration is as follows:

entity GPIO_demo is
    Port ( BTN          : in  STD_LOGIC;
           z            : in  STD_LOGIC;
           A            : in  STD_LOGIC;
           B            : in  STD_LOGIC;
           LED          : out STD_LOGIC;
           CLK          : in  STD_LOGIC;
           UART_TXD     : out  STD_LOGIC;
           COUNT_OUT    : out unsigned(11 downto 0)
              );
end GPIO_demo;

I define these relevant signals in architecture:

type state_type is (S00, S01, S10, S11);
signal state, next_state: state_type;
signal count: unsigned(11 downto 0) := (others=>'0');

My FSM is as follows:

SYNC_PROC: process(CLK)
begin
    if rising_edge(CLK) then
        if ( z='1' ) then
            state <= S00;
            count <= "000000000000";
        else
            state <= next_state;
        end if;
    end if;
end process;

NEXT_STATE_DECODE: process(state, A, B)
begin
    case state is
        when S00 => 
            if(A = '0' and B = '1') then
                count <= "000000000000";
                next_state <= S01;
            elsif(A = '1' and B = '0') then
                count <= "000000000000";
                next_state <= S10;
            end if;
         when S01 => 
            if(A = '1' and B = '1') then
                count <= "100000000000";
                next_state <= S11;
            elsif(A = '0' and B = '0') then
                count <= "100000000000";
                next_state <= S00;
            end if;
         when S11 => 
            if(A = '1' and B = '0') then
                count <= count - 1;
                next_state <= S10;
            elsif(A = '0' and B = '1') then
                count <= count + 1;
                next_state <= S01;
            end if;
         when S10 => 
            if(A = '0' and B = '0') then
                count <= count - 1;
                next_state <= S00;
            elsif(A = '1' and B = '1') then
                count <= count + 1;
                next_state <= S11;
            end if;
    end case;
    COUNT_OUT <= count;
end process;

Any idea on why this output does not update?

Wally
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    Hello and welcome to SO. I suggest you update the question to make it an [MCVE](https://stackoverflow.com/help/minimal-reproducible-example). I note your `count` signal has multiple drivers because it is driven from multiple processes. It needs to only be in the clocked process. In the async process it will not update how you expect. – Tricky Dec 08 '22 at 22:26
  • In addition to multiple drivers assigning a signal to increments or decrements of the signal value should only occur within a clock edge condition. At best otherwise you have a gated oscillator. An increment or decrement provides feedback, delay (at least one delta cycle) and inversion of at least one element. Note you're missing count from the sensitivity list which means simulation won't match synthesized behavior. – user16145658 Dec 08 '22 at 23:12

0 Answers0