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Questions tagged [flip-flop]

Flip-flops (FFs) are electronic devices with two stable states. They are the simplest system capable of storing one bit of information.

Anything related to flip-flops (FFs). FFs are bistable electronic devices, i.e. devices which exhibit only two stable states. As such, they can be viewed as the simplest system capable of storing one bit of information without additional circuitry.

See Wikipedia page on flip-flops.

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Simulate Flip-Flop D ISim 12.3

How can I simulate this vhdl code on ISim 12.3? I know it works because I downloaded to the FPGA but I cannot see a good simulation. Thanks in advance and sorry if it's too basic but I'm very new to this. library IEEE; use…
BRabbit27
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Minimal number of D flip-flops

I have encountered the following question and can't be sure on the answer. Do you have any suggestions, any help would be much appreciated. The Fibonacci sequence F(n) is defined by F(1)=1, F(2)=1, and Fn=F(n-2) + F(n-1) for all integers n>= 3.…
serkank
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Design A Circuit That Can Detect 4 Consecutive 1'S. Draw State Diagram & State Table

Using the design procedure for sequential circuits, we have to design a circuit that can detect 4 consecutive 1s or more, there was a similar question but with 3 consecutive 1s or more, in that question, we had to make a state table and diagram with…
Qartzai
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CLOCK_DEDICATED_ROUTE error in creating an RS latch

I am trying to describe a RS asynchronous latch in VHDL. I receive this error from vivado. [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the…
Marcu Petric
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Number of flip flops generated in Verilog code

How can you determine the amount of flip flops that will be generated during synthesis without using any tool? This first code is supposed to create 5 flip flops module regdesp (PL, RST, ENSERIE, CLOCK, ENPARA, SALSERIE); input PL; input…
Jhon
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Finding the result after N clocks states

This is the diagram of 5 D flip-flops. At first, EDCBA = 00000, after 6 clock beats, EDCBA = ? I drew the timeline values of E, D,C,B,A but got the wrong result. My teacher told me that the answer is EDCBA = 01111. but I got 11110. Please help me…
Việt Anh
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This says its having two 2bit inputs so how to find the truth table

Question 2 A logic circuit is given two 2-bit binary numbers A and B as its inputs. The circuit consists of two outputs Y1 and Y2. The output values of YI and Y2 are obtained as follows: If A
nishitha christopher peiris
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How to simplify sequential logic design by eliminating nested if-else statements

I have a design I've implemented using vhdl that is triggered based on a clock that sends an input signal to one of 8 output channels based on the sel input and also another 2 bit input. The elaborated design shows a lot of nesting due to the many…
Tellrell White
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If the PC register is simultaneously read and written, does its read data contain the previous data or the newly-written data?

If the PC register is simultaneously read and written, does its read data contain the previous data or the newly-written data? Based on my understanding of sequential circuits, the effect of the write command does not instantly take effect in the PC…
marshblocker
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How to simulate circuit of logic gates and flipflops

I'm currently learning C# and WPF, and i'm trying to simulate a circuit of logic gates and flipflops, but it won't work. Could someone please show me a possible way to achive this? (maybe a simple similar application?) What i have tried so…
user15505133
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Multiple Flip Flop device

I'm trying to write a VHDL code that represents an image diagram. I'm new to VHDL so I used a lot of conditionals for it to work. However, I'm having problems with the preset and clear inputs, I used if and elsif in order to know which one preset or…
Laura
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How to make 4 bit ring counter with 4 flip flops?

I have this 4 bit ring counter that I'm trying to make, and I feel like I'm so close, but I can't figure out how to make one input depend on the previous state's output. Here's what I have: `default_nettype none // Empty top module module top ( …
ItsBigBrainTime
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FSM for long bit sequence

Currently, I'm working on a mealy fsm that detects a 17 bit sequence 10100001010000001. Due to the length of the sequence, I'm having difficulty figuring out which state to return to when the input doesn't allow me to move on to the next state. Any…
Tellrell White
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Vivado Error named: [Synth 8-6859] multi-driven net on pin

module top( input [59:0] first, input [59:0] second, output out ); wire [14:0] out_wire; assign first[19:0]= 20'b1111111111111111111; assign first[39:20]= 20'b0000000000000000000; assign…
zaki
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write a verilog for D FF

I want to write a behavioral verilog code for a FF with the following characteristics as shown in the picture. module DFF ( D, CK, RN, Q ); input D, CK, RN; output reg Q; always @ (posedge CK) begin if ( RN==1'b0 ) Q <= RN ; if ( RN==1'b1 ) …
zaki
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