Stack Overflow
Stack Overflow

Questions tagged [flip-flop]

Flip-flops (FFs) are electronic devices with two stable states. They are the simplest system capable of storing one bit of information.

Anything related to flip-flops (FFs). FFs are bistable electronic devices, i.e. devices which exhibit only two stable states. As such, they can be viewed as the simplest system capable of storing one bit of information without additional circuitry.

See Wikipedia page on flip-flops.

148 questions
0
votes
0 answers

Writing to the register at the falling clock edge: Problem in the code

I wrote the Verilog code for a register file having 4 registers (each 32 bit). Expected Outcome Write to the register file should take place at the falling edge of the clock. The clock passed to register file is regClk (gated clock). Please ignore…
Vipin Baswan
  • 11
  • 1
0
votes
3 answers

Why do incomplete if statements create latches during synthesis in VHDL?

Why is it when we try to synthesize incomplete if statements in VHDL the synthesizer uses latches instead of flip-flops? An explanation from a digital/circuit standpoint would be greatly appreciated.
Norbert
  • 115
  • 4
0
votes
1 answer

Register type variable gives error : unknown type

I'm making a 1 bit positive edge Dflipflop. All outputs should be assigned only when there is a positive edge of the clock signal. Q is same as D, Qbar is the negation of D. It somehow works when I try this with Qbar as a wire. assign Qbar =…
YashSeeta
  • 63
  • 3
  • 9
0
votes
1 answer

What book should I refer for flip flop timing diagram for VLSI (for such question given below)?

enter image description here I am pursuing masters in electronics system design and this was my question paper for today exam was unable to answers the first three questions properly.
Varun
  • 21
  • 7
0
votes
1 answer

shift register using dff verilog

I want to create a shift register using d-flip-flop as basic structural element. code: dff: module dff(d,q,clk,rst); input d,clk,rst; output reg q; always @(posedge clk) begin:dff_block if(rst==1'b1) q=1'b0; …
Sun Voyager
  • 147
  • 2
  • 12
0
votes
2 answers

Verilog d flipflop circuit testing

I'm trying to construct a structural implementation of a circuit that consists of a d flipflop, it has inputs x and y, x and y are exclusive or'd and that result is exclusive or'd with the current state, and used as the input to the d flip flop. and…
dshawn
  • 327
  • 1
  • 12
0
votes
1 answer

T flip flop VHDL code

I am learning VHDL and I ran into the following code: Entity fft is port (t, r: in bit; q: out bit); End entity; Architecture fft_df of fft is signal state: bit :='0'; Begin state <='0' when r='1' else not state when t='0' and…
michele_ub
  • 125
  • 1
  • 7
0
votes
1 answer

Confused with this Kmap

Its a 3 variable kmap ABC, I need to solve this for the design of a JK counter and I'm stuck on how to solve this? please help
El CC
  • 77
  • 2
  • 9
0
votes
1 answer

How to implement hardware that remembers previous value in digital logic design?

I am trying to design the following: The datapath of an octal calculator which has a 24-bit input register in reg and a 24-bit accumulator acc. The contents of both registers are displayed as eight octal (radix-8) digits. Both are cleared on…
aa1
  • 783
  • 1
  • 15
  • 31
0
votes
1 answer

Issue with Synchronous Sequential Circuit using Flip Flop D

Right now i'm working on a project concerning the use of D Flip Flop on Falling Edge, with x and y being the inputs and z being the output. The Circuit will only give z ='1' only if x and y are both 0 and also if they were both 0 in a previous clock…
Luisito
  • 36
  • 7
0
votes
1 answer

FSM Mealy Machine Sequence Detector. How to use multiple flip flops?

Right now I am working on a small project in Vivado, a Mealy FSM. The program must detect a 6 bits sequence 001011, and output "1" when the sequence is detected. The code concerning the sequence detection is doing just fine, but besides that, it…
Luisito
  • 36
  • 7
0
votes
2 answers

how does vhdl guarantee timing constraints

my question is, imagine you have counter, having output connected to register. Now on falling/rising edge of clock register (FF) stores data and counter generates new data, but what if counter is really fast and data arrives at register's input in…
Zhani Baramidze
  • 1,407
  • 1
  • 13
  • 32
0
votes
2 answers

SystemVerilog: S-R Latch doesn't work correctly

Here is my gate-level description of an S-R latch: module SR_Latch_Nand(input S, R, C, output Q, QB); wire s1, r1; nand #8 n1(r1, R, C); nand #8 n2(s1, S, C); nand #8 n3(QB, R, Q); nand #8 n4(Q, S, QB); endmodule and here is test bench…
Ju Bc
  • 173
  • 2
  • 11
0
votes
1 answer

VHDL how to generate multiple flip flop entities to use BIT_VECTOR as D-input

I am trying to use the generate function to make multiple flip flops to be used a register. I have a signal bit vector which i would like each bit to be the D input into its equivalent flip flop but after compiling i get the warning that the output…
Eddy Herman
  • 21
  • 6
0
votes
1 answer

flip-flop-operator/readline-counter question

Reading this Perl: extract rows from 1 to n (Windows) I didn't understand the flip-flop-operator/readline-counter part. perl -nE 'say $c if $c=1..3' my_file 1 2 3E0 Could someone explain me more detailed where this output comes from?
sid_com
  • 24,137
  • 26
  • 96
  • 187
1 2 3
…
9 10