Questions tagged [flip-flop]

Flip-flops (FFs) are electronic devices with two stable states. They are the simplest system capable of storing one bit of information.

Anything related to flip-flops (FFs). FFs are bistable electronic devices, i.e. devices which exhibit only two stable states. As such, they can be viewed as the simplest system capable of storing one bit of information without additional circuitry.

See Wikipedia page on flip-flops.

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SystemVerilog 2-bit register decoding problem

I have two 2-bit inputs and an output of 1-bit. So what I'm trying to do is code a next state value with taking AND of the two inputs, then use non-blocking <= to assign that value into register xy_r, which is now two D-flipflops. So I am seeking to…
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Two module verilog is not working

module rff_try_1(q,inp,clk); input clk,inp; output q; reg q; DFF dff0(q,inp,clk); endmodule module DFF(q,inp,clk); input inp,clk; output q; reg q; always @ (posedge clk)begin if(clk)begin q=inp; end end endmodule here I'm using two modules but…
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Verilog D-Flip-Flop not re-latching after asynchronous reset

I have a flip-flop with an asynchronous reset and an enable. Here is my code: module DFF_aSR(in, enable, clock, reset, out); input in, enable, clock, reset; output out; reg out; always @ (posedge clock or posedge reset) begin if (reset) begin …
MMP
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Dealing with logic gates, how do I build a circuit from k-map equations?

My partner walked off with the sheet so I can't provide you with the table but I have the 6 supposed equations. I need to build a 3-bit up-counter with JK flip-flops. Following are the equations: J(Q1) = ~Q1 * Q0 K(Q1) = Q1 * Q0 J(Q2) = Q2 *…
Milan Novaković
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How do you feed a file into memory made from custom modules (no reg) like with readmemb?

For example, instead of using reg [3:0] RAM [0:31]; I've made my own module attempting to use using a hardwired FlipFlopMod. This is what I'm trying to do (but you'll see it obviously doesn't work): module mem_mod(addr, mem_out); input [4:0]…
trusktr
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Counter With Frequency divider is not incrementing

The following code is written for an asynchronous counter. The program compiles fine but the counter value doesn't increment after 1. What am I doing wrong? Here is the code: //TOP module CounterWithDivider(clk,reset,temp,q); input…
James Aflred
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In Perl can i apply 'grep' command on the data i captured using flip-flop operator directly?

I need to find the 'number' of occurrences of particular words (C7STH, C7ST2C) that come in the output of a command. The command starts and ends with a 'fixed' text - START & END like below. This command is repeated many times against different…
pkr13
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Counting high of p showing average on d

module try2(p,d,q1,q2,q3,q4,q5,q6,q7,q8,c,a); input p,c; output [15:0]q1,q2,q3,q4,q5,q6,q7,q8,d,a; reg [15:0] d=16'b0;//may be error reg [15:0]a; always @ (posedge p) begin d<=d+1; end DFF dff0(q1,d,p); DFF dff1(q2,q1,p); DFF dff2(q3,q2,p); DFF…
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Exporting part of a circuit from a circuit defined as structural netlist in verilog

I have a gate-level structual netlist of a design with 40,000 gates and 5000 flipflops in verilog. It is a flattened netlist with no sub-circuits inside. I would like to extract another netlist from this large netlist by deleting a few flip-flops…
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How to create a 4-bit circular shift register which shifts by 2 bits?

Question: Create a 4-bit circular right shift register. If the number is odd then it will shift 1 bit and if the number is even then it will shift 2 bits. Input: 1110 (even number) 1st clock pulse: 1011 2nd clock pulse: 1110 I have created the 4-bit…
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Racing/ S-R Circuits?

Following truth table resulted from the circuit below. SR(NOR) latch is used. I have tried several times to trace through the circuit to see how truth table values are produced but its not working. Can someone explain to me what is going on ? This…
Jenna Maiz
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Verilog: Implement a Pipeline hardware using flipflops

How to create a simple one stage pipeline in Verilog?
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