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Questions tagged [flip-flop]

Flip-flops (FFs) are electronic devices with two stable states. They are the simplest system capable of storing one bit of information.

Anything related to flip-flops (FFs). FFs are bistable electronic devices, i.e. devices which exhibit only two stable states. As such, they can be viewed as the simplest system capable of storing one bit of information without additional circuitry.

See Wikipedia page on flip-flops.

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4-bit Shift register with flip flop

I want to build a 4-bit shift register using D FlipFlop , but I don't understand this diagram. This code is given to me for shift register ENTITY shift4 IS PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; Enable : IN STD_LOGIC; Sin : IN STD_LOGIC; …
Manuel Pap
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Quartus D Flip Flop with asynchronous reset

I need a DFF with asynchronous reset in my diagram. Does quartus have it? If not, how can I implement it?
Feri
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I'm struggling with writing the truth table for this state diagram for jk flip flops

I need help in understanding the above state diagram.
user4306253
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Can a D flip flop be enabled this way?

Here is a D flip-flop with a CLOCK ENABLE input. click here, I am new, can't post images yet, sry This makes me wonder. Why not just AND gate the CLOCK and the CLOCK ENABLE inputs and output this to the flip flop clock input. I feel like I cannot do…
Vain
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T Flip Flop with clear (VHDL)

I'm having problems coding a T Flip Flop with clear and reset. As the picture below shows, t_in is operating as enable input, that will be set to 1 or 0 from a mod-m counter. to_ldspkr will then toggle. The clr_FF will clear the flip flop. Link to…
user2263752
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verilog instantiate multiple registers

I have writen an 8bit register module like this: module ff_8 #( parameter q0=0 )( input clk, input rst_n, input enable, input [7:0] d, output reg[7:0] q, ); always @ (posedge clk) if (!rst_n) begin q <= q0; end else…
k k
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2 Bit Counter using JK Flip Flop in Verilog

I'm writing verilog code of 2 Bit Counter using JK Flip Flop that counts 0-3 and back to 0. I'm using Xilinx EDA. However I'm keep getting one error and I don't know what it means? The line numbers doesn't show up here, but error is located at…
Eduardo Romero
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Correct way of modelling a Flip Flop

I was going through a document from Microsemi website (Actel HDL Code) and I found a few implementations of flip-flop (Synchronous, Asynchronous etc.).In all the cases the author has modelled the flip-flops with blocking statements. I want to know…
chitranna
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In a JK Binary Counter from 0 to 9, why is the NAND gate connected to the second and fourth J-K flip flop and not the first and fourth?

In a binary counter design using 4 J-K flip-flops, that counts from 0 to 9, the flip flops are reset when the output from the 2nd flip flop NAND the 4th flipflop equals to 0. Since binary 9 is 1001, why is the NAND connected to these 2 outputs and…
user3001845
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S-R Flip-Flops (Unlocked)

The operation of S-R latches is confusing me. From what I can tell, the outputs, Q and Q' are determined by: Q = R NOR Q' Q' = S NOR Q Where S and R are two input bits: set and reset. I don't quite understand how both outputs are defined in terms…
Victor Brunell
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Synch / asynch d-type flip flop in vhdl

I've some problems with VHDL's configuration. I should make a simple D-TYPE FLIP FLOP with two different architectures. One should be synchronous and the other asynchronous. The code of the entity is entity FD is Port ( D: In std_logic; CK:…
LyB8899
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Verilog: trying to blink leds in series using a clock divider at multiple frequencies

I'm trying to use two switches to select the frequency I want to blink the led's at. My verilog code is as follows: `timescale 1ns / 1ps module clk_divider( input clk, input rst, input [1:0] sw, output led ); reg…
ElectricalEngineerInTraining
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Cleanest way to generate 8-neighbour coordinates

I'm looking for a way to generate the following sequence of numbers (which are the relative coordinates of a pixel's 8 neighbours, starting with the north-west pixel and ending with the west). The first number is the y-coordinate and the second is…
user2398029
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D-latch time diagram with preset and clear?

I'm trying to study for an exam and I've been searching for any videos or images or pages explaining the time diagram for the D-Latch that involves the preset and clear. I'm finding a lot of results for the D flip-flop but not just the D-latch.…
user16951674
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T flip flop won't produce outputs

I have made some verilog code and a test bench to create a T flip flop but cannot get the outputs to change to anything other than x. I've tried doing o/p as reg in the module and the testbench and then assigning the tb reg to a wire but didn't…
Darius
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