Vivado Error named: [Synth 8-6859] multi-driven net on pin

Question

module top(  
input [59:0] first,   
input [59:0] second,   
output out
        ); 

wire [14:0] out_wire;

assign first[19:0]= 20'b1111111111111111111;  
assign first[39:20]= 20'b0000000000000000000;  
assign first[59:40]=20'b11001100110011001100;

 .....
 ... 
 ..

I am getting the error in the title when synthesizing if I include the assign statements. How do I initialize these 3 assignment values to first[59:0] properly?

The whole design is combinational.

score 3 · Answer 1 · answered Jan 11 '20 at 08:45

You say

You want to inialise the values.
The whole design is combinational.

That is contradictory. Combinational signals always have a value assigned to them. you can't initialise them, not even with an initial statement.

Thirdly: Your first is an input.
If you want to assign a value to that it must be done outside the module. Thus you must make sure that whatever is driving your 'first' has the correct initial value. If that is a testbench you have to solve the problem there.

Vivado Error named: [Synth 8-6859] multi-driven net on pin

1 Answers1