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Questions tagged [flip-flop]

Flip-flops (FFs) are electronic devices with two stable states. They are the simplest system capable of storing one bit of information.

Anything related to flip-flops (FFs). FFs are bistable electronic devices, i.e. devices which exhibit only two stable states. As such, they can be viewed as the simplest system capable of storing one bit of information without additional circuitry.

See Wikipedia page on flip-flops.

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signal drops to undefined while all related signals are defined

I am writing a process that has to look for every incoming bit, keep track of wether or not the total amout of ones received is 1 and, when the time comes has to compare the value to a reference value. The process is the following: parity_tester :…
Cheiron
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How to create relative placement of Flip-flops in Microsemi/Actel Libero?

In the past I've used some Xilinx FPGAs and was able to easily create RELATIVE placement of flip-flips using VHDL attributes such as RLOC. Currently I'm working with the SmartFusion2 FPGA and trying to achieve the same in Libero SoC. After looking…
Ethan
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How to avoid red error lines (JK FlipFlop as subcircuit ) [Logisim]

I have build a JK FlipFlop in Logisim to further use it as subcircuit. The Problem is that when you place that subcircuit it will start with the red colored exit pins. The FlipFlop is also depending on the information of the state of the outputs, 1…
Philip
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Flip Flop JK always returns X

I want to design a JK flip flop. I wrote the code, but when I run it, it always returns x. Here is the test module just for testing: `timescale 1ns / 100ps module flipflopJK(input j , k , r , s , clk , output q , nq);//nq = not q -- r=rest -- s=set…
destrat18
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DFF Testbench confusing

So i saw this VHDL code for a testbench for a DFF somewhere and i don't quite get a few things. 1) Why are there 5 cases? Why aren't there just two? when the input is 0 and when it is 1; 2) Why did he pick those waiting periods so randomly? It seems…
gliga bogdan
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Verilog DFF Simulation Producing x for Output

This should be the simplest issue to sort out but for some reason I just can't figure it out. I'm currently teaching myself Verilog and as an exercise have been developing very basic modules and test benches for these modules. One of these modules…
nslogan
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How Can I Modify This D-FF For Generic Setup/Hold Times?

I have coded the following negative-edge triggered D-FF below: ENTITY d_ff IS PORT (d, cl : IN BIT; q, qbar : INOUT BIT); END d_ff; ARCHITECTURE dataflow of d_ff IS BEGIN PROCESS (clk) IF (clk = '0' AND clk'EVENT) q <= d; ELSE q <= q; …
Rome_Leader
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Shift Register Design using Structural Verilog outputs X

I am designing a shift register using hierarchical structural Verilog. I have designed a D flip flop and an 8 to 1 mux that uses 3 select inputs. I am trying to put them together to get the full shift register, but my output only gives "XXXX"…
Riley
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Programming a ripple counter in C with JK flip flops

I've decided to have a go at programming flip flops in C. I've had an attempt at both a D and JK flip flop (without preset and clear sections yet). I'm testing if by cascading them, I can get them to produce a simple 4 bit ripple counter. After…
Pyrohaz
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No output from a pattern matching module

The objective is to write structural Verilog code for a circuit that has two inputs, w1 and w2, and an output, q. The circuit compares the input sequences of w1 and w2. If w1 and w2 match for 4 consecutive clock pulses, q should be 1; otherwise it…
jeebface
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Structural Verilog) creating a mod-12 counter with 4 D-FF - no outputs from some FFs

I'm trying to make a mod-12 counter in Verilog using 4 D-FFs. I've actually come up with two implementations, one of which works as intended (but is really bad practice IRL), and the other does not work as intended. The following is the…
jeebface
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VHDL Define a signal when undefined

So, I've been working on some VHDL homework and I'm having some trouble with my testbench. Basically, my testbench is running through the different possibilities for a number of flip-flops. However, I keep getting 'U' as a result from one of the…
Cameron Simpson
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Use of Set in a Flip Flop

1)I understand that reset is used in ASIC to start from a known state. Like always @ (posedge clk or negedge reset) begin if (reset) //Initialize the signals else //do something end But if this is the case , why don't we use set signal and start…
chitranna
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Undesiderated 1-bit latch (VHDL)

I'm programming a N-bit non-restoring divider, but I faced a little problem. I have an Operative Part (combinatorial) and a Control Part (Finite State Machine). The Control Part has a 2 processes FSM, 1 for updating the next state and 1 for the…
HBv6
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Perl Flip-Flop operator - Global State Issue?

I am doing some text parsing using flip-flop operator and my data looks like below: COMMAND START CELL 123 COUNTER1 COUNTER2 COUNTER3 23 25 45 COUNTER1 COUNTER2 COUNTER3 22 34 52 CELL 234 COUNTER1…
pkr13
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