Number of flip flops generated in Verilog code

Question

How can you determine the amount of flip flops that will be generated during synthesis without using any tool?

This first code is supposed to create 5 flip flops

module regdesp (PL, RST, ENSERIE, CLOCK, ENPARA, SALSERIE);

   input PL; 
   input RST; 
   input ENSERIE; 
   input CLOCK; 
   input[3:0] ENPARA; 
   output SALSERIE; 

   logic SALSERIE;
   logic [3:0] SHIFT; 

   always_ff @(posedge CLOCK or negedge RST)
      if (!RST)
         SHIFT <= 4'b0000 ;
      else
         if (!PL)
            SHIFT <= ENPARA ;
         else
            begin
                    SHIFT[3] <= ENSERIE ;
                    begin : xhdl_0
                    integer i;
                    for(i = 2; i >= 0; i = i - 1)
                    begin : DESPLAZAR
                            SHIFT[i] <= SHIFT[i + 1] ; 
                    end
                    end 
                          SALSERIE=SHIFT[0];
            end
endmodule

This second example creates 32 flip flops

module SHIFTER2D(clock,reset,clear,shift,entrada_serie, salida_serie); 

parameter tamanyo=4; 

input clock; 
input reset; 
input [7:0] entrada_serie; 
input clear; 
input shift; 
output [7:0] salida_serie ;
 
logic [tamanyo-1:0][7:0] aux; 

always_ff @(posedge clock or negedge reset) 
if (!reset) 
    aux<={tamanyo{8'b0}}; 
else 
    if (!clear) 
        if (shift==1'b1) 
            aux<={entrada_serie,aux[tamanyo-1:1]}; 
    else 
        begin
            aux[tamaño-1]<= entrada_serie; 
            aux<={tamanyo{8'b0}}; 
        end 

assign salida_serie=aux[0]; 

endmodule

I want to understand how can you tell from the code that 5 and 32 flip flops will be generated when the code is synthesized.

score 0 · Answer 1 · answered Nov 06 '22 at 23:47

0

Count the number of bits that are assigned to in clocked processes.

First example

SHIFT: 4 bits
SALSERIE: 1 bit

Total: 5 bits

Second example

aux: tamyano times 8 bits

Given tamyano is 4, that's 32 bits.

answered Nov 06 '22 at 23:47

mkrieger1

19,194
5
54
65

score 0 · Accepted Answer · answered Nov 07 '22 at 16:27

In general, in SystemVerilog, all the signals that are assigned (signals that are in the left hand side of a blocking = or nonblocking <= assignment), inside an always_ff process will be synthesized into Flip Flops. So... in your first example: SHIFT (4bits) and SALSERIE (1bit) are assigned inside an always_ff process. Therefore 5 flip flops will be synthesized.

In your second example, only aux (4x8 = 32bits) is assigned inside an always_ff block, therefore 32 Flip Flops will be synthesized.

WARNING: in your first example code, A) SALSERIE is not reset (it's not assigned to 1'b0 or 1'b1 under the if (!RST) clause. You should reset (unless you know what you're doing) all the signals that will synthesize into a flip flop. B) you assign SALSERIE using a blocking = assignment. In general this is not a good idea, use blocking assignments <= inside always_ff blocks.

Number of flip flops generated in Verilog code

2 Answers2

First example

Second example