write a verilog for D FF

Question

I want to write a behavioral verilog code for a FF with the following characteristics as shown in the picture.

module DFF ( D, CK, RN, Q );
input  D, CK, RN;
output reg Q;

always @ (posedge CK)
begin
if ( RN==1'b0 )
  Q <= RN ; 
if ( RN==1'b1 )
     Q <= D ;
if RN

I DONT KNOW WHAT TO WRITE HERE

end

    );
endmodule

score 2 · Answer 1 · answered Jan 06 '20 at 10:35

2

From your function table, RN seems to be treated as an asynchronous input. In that case, negedge RN should also be added to the sensitivity list. The remaining is the same as @Serge's answer.

always @(posedge CK or negedge RN)
    if (RN == 1'b0)
        Q <= 1'b0;
    else
        Q <= D;

answered Jan 06 '20 at 10:35

Hiroto Kagotani

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Could I have written the condition here as if (! RN) instead of if (RN == 1'b0) to have the same output? – zaki Jan 08 '20 at 05:24
Yes. `(RN == 1'b0)`, `(! RN)` and `(~RN)` for 1-bit wire RN are identical. – Hiroto Kagotani Jan 08 '20 at 14:01
One last thing, how do I know that I have to use negedge RN? Why negedge? I don't see anything in the truth table showing sensitivity to negedge..sorry might be a dumb question.. – zaki Jan 08 '20 at 19:29
Your truth table says Q is 0 whenever RN is 0. This means you need to reset Q as soon as RN gets 0, that is `negedge RN`. This is an idiom frequently used in Verilog for asynchronous resets and worth remembering. – Hiroto Kagotani Jan 09 '20 at 05:13

Serge · Answer 2 · 2020-01-04T20:20:45.993

1

There is nothing to write there. It is easier, like the following:

always @(posedge clk)
   if (RN == 1'b0)
       Q <= 1'b0;
   else
       Q <= D;

The only way the Q can be changed is at the posedge of clk. So, your last row in the table is fulfilled here.

The rest is obvious, and you almost got it in your code.

You can use RN as rhs in your code, but it limits flexibility and usually constants are used there.

edited Jan 04 '20 at 20:20

answered Jan 04 '20 at 20:13

Serge

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Thank you. From what I understand, the last row states that when RN=1 for falling edge CLKs the output will be unchanged. I want to understand why is it "RN"? Does it stand for Reset - negative? There should be a negatively edge triggered concept here somewhere? I took this from a manual so I am confident the term "RN" must mean something. – zaki Jan 05 '20 at 03:12
it is just a name of a variable. You probably guessed right for the abbreviation. ResetNegated looks like a possibility. And yes, there is a concept of `negedge` as well. – Serge Jan 05 '20 at 03:27
But how so? negeedge isn't doing anything in this case right? that's why it feels like I am missing something. – zaki Jan 05 '20 at 03:30
Sorry I am having a hard time to understand how this last case is captured by this code. – zaki Jan 05 '20 at 03:38
according to your table, negedge is supposed to do nothing. The old value og 'Q'should be preserved. This is exactly what is done in simulation: only the `posedge` is used for simulation of this block, as specified in its sensitivity list. The block just does not react to the negedge at all. Synthesis tools recognize this style and synthesize a hardware ff. – Serge Jan 05 '20 at 03:44
Do you agree with Hiroto Kagotani 's answer? – zaki Jan 06 '20 at 20:14
Yes, it looks like an `asynchronous` reset, because the first row in the table does not depend on the clock edge. Otherwise it would've been specified. So, Hiroto is correct. My example shows a `synchronous` reset. – Serge Jan 06 '20 at 21:23

write a verilog for D FF

2 Answers2