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Questions tagged [flip-flop]

Flip-flops (FFs) are electronic devices with two stable states. They are the simplest system capable of storing one bit of information.

Anything related to flip-flops (FFs). FFs are bistable electronic devices, i.e. devices which exhibit only two stable states. As such, they can be viewed as the simplest system capable of storing one bit of information without additional circuitry.

See Wikipedia page on flip-flops.

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Verilog instantiation error

I'm having an issue simply calling a module for a JK flip flop. Our project is to make a state machine, and My logic is correct, but i'm getting an error that says "VHDL module instantiation error: can not connect instance ports both by error and…
Tough Griff
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What does "Illegal reference to net error" mean?

I wrote this code for a T Flipflop. The output is toggled at every 11th clk. The program is giving me this error: Illegal reference to net "clkDivider" What does this error mean? What is causing it? Here is the code: module…
James Aflred
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Divide a clock by 3 without changing the duty cycle?

I searched a lot but I didn't find a good solution. Most answers work only when the duty cycle is 50% but I am searching for a solution that works for clocks with duty cycles like 40%, etc.
CoderInNetwork
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flip-flop, latch basic concept

i hope someone could help me with this. I can't get the point of the utility of flip-flops, the point of saving the state. If we want to save the previous state, why don't we simple maintain the inputs as they are. In general why is not this way :…
t0ma5
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Undefined output of Ring Counter Test waveform

I have modeled 4 bit Ring Counter using D Flip Flop. The D flip flop is in separate file, included in my workspace. The D flip flop works correctly (gives correct output waveform). This is the code of ring counter: library ieee; use…
Vinayak Garg
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Error : Identifier 'q' is not readable in architecture of T Flip Flop

I am trying to model a T Flip Flop using VHDL. library ieee; use ieee.std_logic_1164.all; entity tff is port ( clk: std_logic; t: in bit; q: out bit; qbar: out bit); end tff; architecture tff_arch of tff…
Vinayak Garg
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minimal number of d flip-flops required for first seven Fibonacci numbers

I encountered a problem while preparing for a test. What is the minimal number of d flip-flops required (along) with combinational logic to design a counter circuit that outputs the first seven Fibonacci numbers and then wraps around? A) 3 B) 4 C)…
user966892
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Trying to design an 8-bit reloadable down counter

Task: Designing a 8-bit downcounter which takes an initial input value and start the downcount, and when count becomes 8'b0000_0000, it should automatically set to input value. Ex: If given input is 8'b10010100, counter should start counting down,…
Sunil.B
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Edge triggered flip flop behaving like a transparent latch when sensitivity list has two rising edges

Trying this on a Terasic DE10-Lite, programmed with Quartus Prime Lite Edition. SW[0] is a switch. LEDR[0] is an LED. KEY[0] is a push button. The push button is active low. I want to model a flip flop that stores SW[0] in register r0 and displays…
user20828066
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JK-Flip Flop: K-Map to find the Value of Next State (Qn+1)

Given the Truth Table, Characteristic Table and Excitation table for a JK Flip Flop. I am doing a K-Map to find Qn+1 (next state) given J, K and current State. The K-Map from a tutorial explaining this is shown below: Why isn't JK' (not K) not…
Ash Rivers
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Register values not showing at the correct time in testbench simulation

Based on research, the input value to a flip flop is read during one rising/falling edge and output at the next rising/falling edge, however, I'm not seeing this behavior in my test bench.What I believe I'm seeing is that the output values are being…
Tellrell White
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Wrong output while modelling JK FF: output is x

I am modelling a JK FLIP Flop using Verilog. I am getting the output q as x in all the cases. I used case statement for various jk combinations. I hardly found any issue with the code. Design module jk_ff ( input j, input k, input clk,…
vu2swz
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JK Flip-flop using D Flip-flop and gate level simulation does not stop

I'm trying to implement a JK flip-flop with a D flip-flop and a gate level, but the problem is that when I run the code, the terminal doesn't show me anything. It's like it has always been calculating but nothing is shown. I need to press crtl + c…
C S
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4-bit synchronous double down counter jk flip flop

Recently, I am trying to learn digital design and Verilog HDL. I am currently working on flip flops. I was trying to construct a 4-bit synchronous double countdown (down counter) with jk flip flop. Ex: 1111 - 1101 - 1011 - 1001 - .. (15 - 13 - 11 -…
exxe
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Unexpected output when creating a JK Flip Flop module using an SR Flip Flop

I have written Verilog modules for SR Latch, SR Flip Flop (by instantiating the SR Latch module), and JK Flip Flop (by instantiating the SR Latch module). I'm using Xilinx Vivado 2019 version for simulation and viewing output waveforms. The SR Latch…
Aditya
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