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Questions tagged [flip-flop]

Flip-flops (FFs) are electronic devices with two stable states. They are the simplest system capable of storing one bit of information.

Anything related to flip-flops (FFs). FFs are bistable electronic devices, i.e. devices which exhibit only two stable states. As such, they can be viewed as the simplest system capable of storing one bit of information without additional circuitry.

See Wikipedia page on flip-flops.

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SystemVerilog Sequential Circuits Coding Style

I am currently working through Pong Chu's FPGA Prototyping By System Verilog Examples, specifically on Chapter 4 which covers sequential circuits. In it, Chu describes the method where a sequential circuit has the sequential part and the…
fpd011
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How to correct this error "Illegal reference to net q"?

I am getting this error when I am compiling my file which Using Behaviour Modelling is designing a positive edge triggered T-Flip-Flop with asynchronous clear in Verilog code. module t_flip_flop (input clk, input pr, input clr, input d, output q); …
Sai Ganesh K
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Why do we have to add a "clr" (clean input wire) while forming a T flip-flop in Verilog with Vivado?

I am trying to form a T flip-flop in Verilog. I am studying verilog from "Digital System Design with FPGA: Implementation using verilog and vhdl" and the code for T flip-flop is here below: module t_flip_flop(t,clk,clr,q,qn); input…
i.just.wacthed.mr.robot
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Flip flop testbench shows incorrect values

I need to implement the testbench for the 4 flipflops module that are in the design.sv interface. The modules foo1, foo2 and bar2 are working properly (you can see this when you run, the expected values are the same as the output values) except the…
Connor
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the simulation output of my JK Flip-Flop just get nothing changed

the following is the jk flip-flop with preset and clear there's nothing wrong after compiling. But after simulation, I just find out that my output (QA, QB, QC, QD) just keep to be 0 and unchanged. is there any thing wrong with my case statement? or…
ginwei
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T flip-flop using dataflow model

I'm trying to simulate the working of t-flipflop. `timescale 1ns / 1ps module t_flipflop( input t, input clk, input clear, output q, output qbar ); wire sbar, rbar; assign sbar= ~(t & clk & qbar & clear); assign rbar= ~(t & clk & q); assign…
trim24
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Do input and output ports behave like flip-flops? (VHDL)

Do input and output ports in VHDL behave like flip-flops, i.e. are they updated on a rising or falling edge of a clock? Here is an example of what I mean. entity main is port( clk : in std_logic; -- FPGA clock x : in std_logic;…
Marko Gulin
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VHDL: Help understanding time steps/states and concurrency

I'm normally a C#/Java programmer and I'm still having trouble fully wrapping my head around hardware description. I have a register that loads in a value. Afterwards, a comparator compares the output of the register with the value '16'. If the…
technokrat
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How can I extract some data out of the middle of a noisy file using Perl 6?

I would like to do this using idiomatic Perl 6. I found a wonderful contiguous chunk of data buried in a noisy output file. I would like to simply print out the header line starting with Cluster Unique and all of the lines following it, up to, but…
Christopher Bottoms
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Initial value of a flip flop on logisim

I am implementing flipflops in logisim. Usually, their output gets back to the circuit as their own inputs. This only works if I manually insert an initial value to the flipflop and then reconnect its output to the input - otherwise, Logisim mark…
francisaugusto
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How many Flip Flops will this code produce?

so I have an exam coming up and I am solving tutes. One of the questions is very basic but I don't think I have the exact logic down for it. It simply gives me a small bit of the code and asks how many Flip Flops will this produce. Could you help me…
bzrk89
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Testbench for T Flip Flop using D Flip Flop in VHDL

I have VHDL codes that of a D Flip Flop, and a T Flip Flop that uses it structurally: it consists of a DFF with D input being T Xored with Q, a clock. But my simulation gives me a waveform that has an output of only a red straight line 'U'. I think…
Rawan Moukalled
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Need help to figure out how the CLB of a FPGA is built (on this drawing)

there is a drawing of a configurable logic block(CLB) of a FPGA I am trying to figure out: (source: eet.com) So, my questions are: 1. What is the green rectangle and what does it do? 2. What is DIN (C2) and EC (C4)? Is EC the same as CE (clock…
genau
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Perl Flip Flop operator and line numbers

I noticed this while looking at another question... If I have a script like this: while (<>) { print if 5 .. undef; } It skips lines 1..4 then prints the rest of the file. However if I try this: my $start_line = 5; while (<>) { print if…
John C
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Verilog shift extending result?

We have the following line of code and we know that regF is 16 bits long, regD is 8 bits long and regE is 8 bits long, regC is 3 bits long and assumed unsigned: regF <= regF + ( ( regD << regC ) & { 16{ regE [ regC ]} }) ; My question is : will the…
baibo
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