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Questions tagged [chisel]

Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.

Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.

Features

  • Hardware construction language (not C to Gates)
  • Embedded in the Scala programming language
  • Algebraic construction and wiring
  • Abstract data types and interfaces
  • Bulk connections
  • Hierarchical + object oriented + functional construction
  • Highly parameterizable using meta-programming in Scala
  • Supports layering of domain specific languages
  • Sizable standard library including floating-point units
  • Multiple clock domains
  • Generates low-level Verilog designed to pass on to standard ASIC or FPGA tools
  • Open source on GitHub with modified BSD license
  • Complete set of docs
  • Growing community of adopters

Resources

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ChiselTest - expect a bit value in a UInt

Per this: https://github.com/chipsalliance/chisel3/issues/2439 I've decided to change all Vec[Bool] to UInt where possible. One feature of a Vec[Bool] is that testing the values of each bit is simple. For example, let's say I have a module that…
nic
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How to write nested fsm in Chisel like SpinalHDL does?

I've found that SpinalHDL has some powerful and elegant ways to describe a rather complicated fsm. I wonder if it's possible to construct a FSM lib (like SpinalHDL has done) in Chisel? p.s. I'm not very familiar with scala.‍️
sheldoncooper0
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How can I test a Chisel3 BlackBox?

I have the following test harness for a module defined in Verilog: class TestMCQDiv extends FlatSpec with ChiselScalatestTester with Matchers { behavior of "MCQDiv" // Dependent Variables for Testing val integerWidth = 50 val…
Espresso
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How to import packages into another package(or files in the same package) using "import" explicitly only once

I'm using chisel based on scala with IntilliJ IDEA. The files in my project are in the same package named mypackage, and I need to import the chisel's library: // file1.scala package mypackage import chisel3._ import chisel3.util._ /** my code */ //…
zaryleik
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How can I generate AHB memory port in Rocket chip

I am trying to implement a Rocket chip SoC design; the SoC design will generate an AXI memory port by default. But I want to use the AHB memory port, and the Rocket chip doesn't have any configs for that. Has someone already done that? thanks
anor
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problem compiling a switch case statement in chisel

I was writing a simple switch-case for my state machine. However, after calling sbt test I receive the following error:
milad hakimi
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How to not synthesize memory for release in Chisel

I'm writing an architecture that makes extensive internal use of SyncReadMem, which is intended to represent SRAM memory banks. Our current synthesis toolchain, however, does not support SRAM properly, but is fine for registers and computational…
Chris
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Verilog generation error without explanation

I am currently trying to create a simple BRAM model from a BlackBox with Chisel version 3.4.3 : class BRamSv (INITFILE: String, NDATA: Int, NDATABYTE: Int) extends BlackBox(Map( "INITFILE" -> INITFILE, "NDATA" -> NDATA, …
escou64
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How is the following chisel statement decoded?

I am learning SonicBoom. The following sentence should be based on the decoding table to assign the corresponding decoding signal. class CtrlSigs extends Bundle { val legal = Bool() val fp_val = Bool() val fp_single =…
Yujie
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How do I connect a client to an IdentityNode with two managers?

The PCIe overlay I'm attempting to invoke connects the two slave/manager nodes to a slaveSide IdentityNode like so: val slaveSide = TLIdentityNode() pcie.crossTLIn(pcie.slave) := slaveSide pcie.crossTLIn(pcie.control) := slaveSide How do I…
metzkorn
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Add a memory to regmap()

I am having a device added to the rocket chip, it has its control & status registers and also an internal ram. To have the ability to access it with software I have added it into the regmap() in the next way : val mem = Module(new…
user3567895
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Can chisel print time like verilog

In digital circuit simulation verification, time is a very important parameter. Verilog can use the $time function to obtain simulation time. I want to know if chisel has the same function.
Self-Motivated Wu
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backend verilator: blackbox module unable to instantiate Chisel-module (generated using emitVerilog)

native verilog module: "my_module". my_module_blackbox is a chisel blackbox corresponding to this module. The native verilog module "my_module" instantiates a RAM(main_ram) that is coded in chisel. The module name is main_ram. The backend used is…
vasantharam
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What do decoupled and irrevocable mean in Chisel?

I frequently see these terms to modify i/o ports within i/o bundles, as in here, but it's unclear what they mean as though this source doesn't directly define them. The chisel-lang docs (as in here) reuse the terms in the definition and aren't too…
Dragonsheep
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How to make verilog is ready for CAD tools after build the VCS simulator

I've built the VCS simulator successfully with some configuration (Default, DualCoreConfig, RoCCExampleConfig etc.) and get the desire files under vism/generated-src Now How Can I use/prepare this file to in CAD-tools (SYNOPSIS) Do I need any…
Riaz Ul Haque Mian
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