Add a memory to regmap()

Question

I am having a device added to the rocket chip, it has its control & status registers and also an internal ram. To have the ability to access it with software I have added it into the regmap() in the next way :

  val mem = Module(new SinglePortMemory(32,128, 7))
  // init //
  mem.io.re := false.B
  mem.io.we := false.B
  mem.io.addr := 0.U
  mem.io.din := 0.S
  val dout = RegNext(mem.io.dout)

  regmap((
        Seq(
          0x0  -> Seq(RegField(1,enable,RegFieldDesc("enable","This bit enable my device")))
          ++ Seq.tabulate(128) {j => 
          (0x50 + (j*4)) -> Seq(RegField(32,
            RegReadFn(ready => {
              when(ready) {
                mem.io.addr := j.asUInt
                mem.io.re   := true.B
              }
              (true.B,dout.asUInt)  
          }),
          RegWriteFn((valid,data) => {
            when(valid) {
              mem.io.addr := j.asUInt
              mem.io.we   := true.B
              mem.io.din  := data.asSInt
            }
            true.B   
          }),
          RegFieldDesc(s"mem_${j}","")
        ))}
      ):_*)

Now this works , but I'm not sure if that is the best way to do that (I mean adding the memory to regmap). Can someone advise on a different / better way to do that ?

Yes I have , it is not shown in the code snippet above, but I do use it. It is being used inside the SinglePortMemory() memory module. — user3567895, Jun 15 '21 at 00:58

score 0 · Answer 1 · answered Jun 18 '21 at 12:44

rocketchip has some built in memories for TileLink and AXI (AHB/APB I don't recall, but can use the others as an example and/or add converters)

https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tilelink/SRAM.scala

You can then connect the new TLRAM to a Xbar in addition to your normal memory mapped registers.

Add a memory to regmap()

1 Answers1