Verilog generation error without explanation

Question

I am currently trying to create a simple BRAM model from a BlackBox with Chisel version 3.4.3 :

class BRamSv (INITFILE: String, NDATA: Int, NDATABYTE: Int)
  extends BlackBox(Map( "INITFILE" -> INITFILE,
                        "NDATA" -> NDATA,
                        "NDATABYTE" -> NDATABYTE)) with HasBlackBoxResource {
  val io = IO(new Bundle() {
    val clock = Input(Clock())
    val reset = Input(Reset())

    val i_p1_en = Input(Bool())
    val i_p1_wen = Input(UInt(NDATABYTE.W))
    val i_p1_addr = Input(UInt(log2Ceil(NDATA).W))
    val i_p1_wdata = Input(UInt((NDATABYTE * 8).W))
    val o_p1_rdata = Output(UInt((NDATABYTE * 8).W))

    val i_p2_en = Input(Bool())
    val i_p2_wen = Input(UInt(NDATABYTE.W))
    val i_p2_addr = Input(UInt(log2Ceil(NDATA).W))
    val i_p2_wdata = Input(UInt((NDATABYTE * 8).W))
    val o_p2_rdata = Output(UInt((NDATABYTE * 8).W))
  })

  setResource("/sv/bram.sv")
}

class BRam (initFile: String, nData: Int, nDataByte: Int) extends Module {
  val io = IO(new Bundle() {
    val b_port = Vec(2, new BRamIO(nDataByte, log2Ceil(nData)))
  })

  val bram = Module(new BRamSv(initFile, nData, nDataByte))

  bram.io.clock := clock
  bram.io.reset := reset

  bram.io.i_p1_en := io.b_port(0).en
  bram.io.i_p1_wen := io.b_port(0).wen
  bram.io.i_p1_addr := io.b_port(0).addr
  bram.io.i_p1_wdata := io.b_port(0).wdata
  io.b_port(0).rdata := bram.io.o_p1_rdata

  bram.io.i_p2_en := io.b_port(1).en
  bram.io.i_p2_wen := io.b_port(1).wen
  bram.io.i_p2_addr := io.b_port(1).addr
  bram.io.i_p2_wdata := io.b_port(1).wdata
  io.b_port(1).rdata := bram.io.o_p2_rdata
}

This code, which previously worked perfectly, is now giving me an error after fully reinstalling my working environment (Ubuntu and sbt 1.5.5):

Elaborating design...
Done elaborating.
[error]     at 
[success] Total time: 5 s, completed Oct 15, 2021, 8:58:09 AM

Even more annoying, no details about the error are given to me when I run sbt run. I never had this kind of error report before reinstallation... And using options like --full-stacktrace or -ll info don't give me more information. Any idea on how to get more hints about the error?

That is an annoying error, I am not able to reproduce with my guess at `BRamIO` and and `bram.sv`, can you provide those files and the main or test that you using to cause the elaboration. — Chick Markley, Oct 15 '21 at 17:42

score 0 · Answer 1 · answered Oct 16 '21 at 06:26

To generate the Verilog, I used with previous versions:

object BRam extends App {
  chisel3.Driver.execute(args, () => new BRam("", 2048, 4))
}

But warnings reminded me that this method is now deprecated, so I replaced it with:

object BRam extends App {
  (new chisel3.stage.ChiselStage).emitVerilog(new BRam("", 2048, 4), args)
}

And now my error is clearly detailed:

[error] (run-main-0) firrtl.transforms.BlackBoxNotFoundException: BlackBox 'sv/bram.sv' not found. Did you misspell it? Is it in src/{main,test}/resources?
[error] null

Thanks Chick Markley for putting me on the trail.

Verilog generation error without explanation

1 Answers1