backend verilator: blackbox module unable to instantiate Chisel-module (generated using emitVerilog)

Question

native verilog module: "my_module". my_module_blackbox is a chisel blackbox corresponding to this module.

The native verilog module "my_module" instantiates a RAM(main_ram) that is coded in chisel. The module name is main_ram.

The backend used is verilator. I.e the code uses chisel peek poke tester, with verilator backend . The native verilog module is unable to locate the module main_ram. The emitted verilog module(main_ram) is present in the directory where I do a sbt run. On the other hand, The blackbox wrap is generated in test_run_dir/<>/. Verilator complains its unable to find main_ram. (Please see error message highlighted below).

Should I get emitVerilog to generate in test_run_dir/<>/.., if yes how? How to get the "directory's" / verilator search-paths right?

Native(hand-coded) verilog module wants to use a chisel generated verilog module and also vice-versa all in the same project. Is such a use-case supported? Are there examples that someone could point to?

More details:-

main_ram is generated using the code below:-

    ```
        (new chisel3.stage.ChiselStage).execute(
        Array("-X", "verilog"),
        Seq(ChiselGeneratorAnnotation(() => new main_ram(data_width,addr_width ))))
    ```

A Blackbox module "my_module.v" attempts to instantiate the main_ram that is generated. Verilator runs into the following Error

       Error:-( replaced real directory names / file names with .../<>):
       cd .../test_run_dir/blackbox920936627 && verilator --cc <>_wrap.v --assert -Wno-fatal -Wno-WIDTH -Wno-STMTDLY -O1 --top-module my_module_blackbox_wrap +define+TOP_TYPE=V<>_wrap +define+PRINTF_COND=!<>_wrap.reset +define+STOP_COND=!<>.reset -CFLAGS "-Wno-undefined-bool-conversion -O1 -DTOP_TYPE=V<>_wrap -DVL_USER_FINISH -include V<>_wrap.h" -Mdir .../ctb/test_run_dir/blackbox920936627 -f .../test_run_dir/blackbox920936627/firrtl_black_box_resource_files.f --exe .../test_run_dir/blackbox920936627/<>_wrap-harness.cpp --trace
       **%Error: .../test_run_dir/blackbox920936627/my_module.v:79: Cannot find file containing module: 'main_ram'**
       main_ram i_ram(clk, rst, write, addr, din, dout, ena);

Following is the Driver/tester code:-

       val works = chisel3.iotesters.Driver ( () => new my_module_blackbox_wrap(parameters), 
           "verilator") {
            c=> new my_module_blackbox_tester(c, parameter)
        }
        assert(works)

Thanks for the help

Answer 1

When you run

(new chisel3.stage.ChiselStage).emitVerilog(new my_module, Array("--help"))

It displays the available options on your terminal. I guess if you want to generate your verilog for the RAM in a specific folder you can use the --target-dir option. Try running the above command and you will be able to see all the other available options.

Also it looks to me that you're generating two separate verilated modules(correct me if I am wrong), one for the RAM module and one for the my_module module. If so, both the verilated modules will have their own main programs in the verilated cpp file. To combine the 2 you will have to remove a lot of code from the main and also rename a lot of classes etc. Basically an API overhaul to combine the 2 modules in the verilated.cpp files. But of course if you want to test out the generated verilog modules through a verilog testbench you can use the above command and generate the verilog where you wish and then write a testbench in verilog to test it.