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Questions tagged [chisel]

Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.

Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.

Features

  • Hardware construction language (not C to Gates)
  • Embedded in the Scala programming language
  • Algebraic construction and wiring
  • Abstract data types and interfaces
  • Bulk connections
  • Hierarchical + object oriented + functional construction
  • Highly parameterizable using meta-programming in Scala
  • Supports layering of domain specific languages
  • Sizable standard library including floating-point units
  • Multiple clock domains
  • Generates low-level Verilog designed to pass on to standard ASIC or FPGA tools
  • Open source on GitHub with modified BSD license
  • Complete set of docs
  • Growing community of adopters

Resources

680 questions
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"Cannot Resolve Symbol" in IntelliJ

I am trying to run scala/chisel code through IntelliJ version 2020.1 using the cloned repository "Chise-template-release". When I attempt to create a new class I received the "Cannot Resolve Symbol" Error. I have confirmed that the JDK…
supernova08
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Adding Ports to a Module/Peripheral using Inheretance

I have a Peripheral which has a general layout as follows. The Block I have mentioned is not designed by me so, I want to inherit the module and make few internal signals as IO ports of the peripheral. The Wire which needs to be converted as the…
hitoswal
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Chisel bootcamp 3.2 Muxes result wrong?

Here is the code in Chisel Bootcamp: Driver(() => new Module { // Example circuit using Mux1H val io = IO(new Bundle { val in_sels = Input(Vec(2, Bool())) val in_bits = Input(Vec(2, UInt(8.W))) val out = Output(UInt(8.W)) …
Phantom
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Error: Attempted to instantiate a Module without wrapping it in Module()

Top module is as follows; class PE (DataWidth: Int, NumLinks: Int, NumEntries: Int, FifoDepth: Int) extends Module { val io = IO(new Bundle { ... }) ... } I think that this is ordinary style for the chisel3. I do the following…
S. Takano
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Changing clocking in RocketSubsystemModuleImp from System.scala

I'm trying to alter the clocks and resets which go to each Rocket tile in my system. At the moment I'm trying to do it like this. In Platform.scala I have some inputs declared in my PlatformIO (where $HARTS is our number of harts): val hart_clocks =…
jbaxter
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How do I run a single UnitTest from rocket-chip?

Specifically I'd like to run AXI4XbarTest from rocket-chip/src/main/scala/amba/axi4/Xbar.scala. It looks this test should be run by the regression tests, but if I go into the regression directory and run export SUITE=UnittestSuite make…
Ben Reynwar
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How to config xLen in rocket core?

I am trying to use rocket core as a baseline core and add some additional features for research purpose, but I can't find where or how to change the value "xLen".
Shibo Chen
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Required: T Chisel Error

I get the following chisel errors for io.out(i) := Cat(io.in1(0) ,io.in2) line. What does it mean? and how do I rectify this? Please help. type mismatch; [error] found : chisel3.core.UInt [error] required: T [error] io.out(i) :=…
Shubha
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How can I modify an int type argument to a T type?

Hello I'm trying to learn chisel and I'm compiling an existing project, but I get a problem with the mem instantiation : How can i modify the int type to type T and what is type T ? Waiting for your answers. Thank you.
HAMZA
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Reverse the input in Chisel3

I want to reverse the input signal in Chisel3. For instance, if the input is 12345678, I want the output to be 87654321. Can anyone please help me with this? Code: import chisel3._ import chisel3.util._ import chisel3.iotesters.{ChiselFlatSpec,…
Rahul
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"data to be connected 'chisel3.core.UInt@103' must be hardware, not a bare Chisel type" when rewrite OpenSoCFabric1.1.2 from Chisel2 to Chisel3

I am trying to rewrite OpenSoCFaric-1.1.2 from chisel2 to chisel3. But I encounter error messages "data to be connected 'chisel3.core.UInt@103' must be hardware, not a bare Chisel type" for below code: File: packettoFlit.scala class:…
Bibo
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Using C++ Emulator fails when calling printf syscall from a RISC-V baremetal program

I'm working on a project based on Rocket-Chip tools. I made a simple baremetal program that works well on Spike (even with multiple cores ...etc). The problem is that when I run it in the C++ Emulator, the latter stops in the first printf call. My…
noureddine-as
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rocketchip emualtor c++ models

Rocketship emulator generates some c++ models/emulators in generated-src folder. Can anyone elaborate what are they? More description would be really helpful I am learning about how chisel generated emulator are helpful for small riscv even without…
ARK91
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How to generate harness in Chisel3

In Chisel2 there's seems to be a way to generate harness judging by this question. It seems that the simulation mechanism is a bit different between Chisel2 and Chisel3. Quoted from the Chisel3 wiki: Chisel2 was capable of directly generating a C++…
Jerry
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Indexing of elements in a Seq of string with chisel

I have, tab=Array(1.U, 6.U, 5.U, 2.U, 4.U, 3.U) and Y=Seq(b,g,g,g,b,g), tab is an array of UInt. I want to do a map on tab as follows: tab.map(case idx=>Y(idx)) But I keep getting the error: found chisel3.core.UInt, required Int. I tried using the…
Foutse
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