Questions tagged [spinalhdl]
13 questions
2
votes
1 answer
How can I make a ternary condition in SpinalHDL?
I would like to make a ternary condition in SpinalHDL as a ternary assignment in Verilog:
e.g.
wire my_condition = (this == that);
wire [1:0] my_ternary_wire = my_condition ? 2'b10 : 2'b01;
desired SpinalHDL code:
val myCondition = this ===…
natanvotre
- 81
- 5
1
vote
0 answers
scala process never finishes in IDEA
When I running a SpinalHDL simulation program, the process is done but never exit. That is, "Process finished with exit code 0" never showed up. I have to shutdown the IDEA to end the process. How is it?
import spinal.core._
import…
Johnhave
- 11
- 2
0
votes
1 answer
combine logical expression for StaticMemeoryTranslatorPlugin used in VexRiscv
I want to use 2 static memory regions for a vexriscv soc using SpinalHdl.
Having very little experience with SpinalHdl and Scala, so maybe I miss a small detail.
I tried this to instantiate 2 StaticMemoryTranslatorPlugins :
plugins ++= List(
…
s vhb
- 1
- 4
0
votes
1 answer
What is the meaning of Masked() in Scala's library SpinalHDL
I have seen many spinal cases using Masked(), but don't truly understand it.
The source code is:
object Masked{
def apply(ml : MaskedLiteral) : Masked = Masked(ml.value, ml.careAbout)
def apply(lit : Any) : Masked = lit match {
case e:…
Pairshoe
- 1
- 1
0
votes
1 answer
Can I use SpinalEnum as field in RegIf?
I want to use SpinalEnum as RegIf field. Here is an example code, which doesn't seem to work:
object SourceEnum extends SpinalEnum {
val src1, src2, src3 = newElement()
}
...
val busif = BusInterface(...)
// Control Register
val ctrl =…
Marek Pikuła
- 75
- 6
0
votes
1 answer
Connecting AXI Stream to StreamFifo
I want connect AXI Stream Master to Stream Fifo. I need only payload, valid and ready signals. Idea is to load FIFO with data and push it via AXI Stream to other part of logic.
Simple example:
case class AxiWithFifo() extends Component {
val io =…
ato1337
- 1
0
votes
1 answer
SpinalHDL ConfigClockDomain not work, how to drive configured clock domain when simulating?
ClockDomainConfig Problem in SpinalHDL
I tried to write a simple spinal HDL demo according to ClockDomainConfig Example to test a configured clock domain and an Area which use the clock domain.
Here is my simple counter:
package mytest
import…
BossWangST
- 31
- 6
0
votes
1 answer
How to write nested fsm in Chisel like SpinalHDL does?
I've found that SpinalHDL has some powerful and elegant ways to describe a rather complicated fsm. I wonder if it's possible to construct a FSM lib (like SpinalHDL has done) in Chisel?
p.s. I'm not very familiar with scala.️
0
votes
1 answer
Is it possible to convert from Bits to SpinalEnum?
I have a SlaveFactory and I'd like to save some flags in registers as SpinalEnums. Is it possible to cast Bits to my SpinalEnum on write operation?
Marek Pikuła
- 75
- 6
0
votes
1 answer
Strange behaviour of yosys on FSM while building for iCE40
I have been toying with SpinalHDL and its SoCs and modules, but came to a general problem - almost none of the code that uses FSMs works. I nailed this issue down to Yosys, which does something weird when it detects a FSM. Here below is a simple and…
pointcheck
- 11
0
votes
1 answer
Giving User-Defined properties for a signal
Disclaimer: I'm not super familiar with Scala. I have used Spinal/Chisel some to test out what I want to do, as well as create some simple HW, so please forgive me if these questions are "entry-level" from a Scala perspective.
I'm planning to use…
l Steveo l
- 516
- 3
- 11
0
votes
1 answer
How to connect a Flow to a Stream in SpinalHDL
I have a write sensitive APB register which shall push into a FIFO with clock domain crossing. I though I would write:
val myFlow = Flow(...)
busCtrl.driveFlow(myFlow,address=4)
val myFifo = StreamFifoCC(...)
myFifo.io.push << myFlow
But the <<…
acapola
- 1,078
- 1
- 12
- 23
-1
votes
1 answer
Vexriscv - implement ram as block ram
How can I generate a Vexriscv core in a way that the generated ram is a vendor specific block ram (e.g. Intel/Altera or Xilinx)?
I tried it by using the black boxing possibility (see…
jodá
- 342
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