Stack Overflow
Stack Overflow

Questions tagged [chisel]

Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.

Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.

Features

  • Hardware construction language (not C to Gates)
  • Embedded in the Scala programming language
  • Algebraic construction and wiring
  • Abstract data types and interfaces
  • Bulk connections
  • Hierarchical + object oriented + functional construction
  • Highly parameterizable using meta-programming in Scala
  • Supports layering of domain specific languages
  • Sizable standard library including floating-point units
  • Multiple clock domains
  • Generates low-level Verilog designed to pass on to standard ASIC or FPGA tools
  • Open source on GitHub with modified BSD license
  • Complete set of docs
  • Growing community of adopters

Resources

680 questions
0
votes
1 answer

Where is top module of rocket processor?

I did a make (make rocket and make project), I met an error at the make project, because I have not yet a target board. So, project file for viva do is not completely generated. I need to add files manually. Where is top module of rocket processor…
S. Takano
  • 313
  • 2
  • 12
0
votes
1 answer

Unable to get the RoCC accelerator built with the default Accumulator example for zed board

Tried building the RoCC accelerator default accumulator example for zed board, but getting an error of "illegal instruction" I tried the below config in the configs.scala file:- class WithAccumRocc extends Config( (pname,site,here) => pname match…
Prashant Ravi
  • 189
  • 12
0
votes
2 answers

Running dummy_rocc_test on zed board

The dummy_rocc_test runs fine on spike with the custom0 instruction but when I put it on the zed board and run it with ./fesvr-zynq pk dummy_rocc_test it gives me an error of illegal instruction. I understand this is because the rocc io is not but…
Prashant Ravi
  • 189
  • 12
0
votes
1 answer

Not sure about what the error messages are trying to convey

I am getting the following error. but I am unable to understand the problem from the error messages printed. run [info] Running HyperCell.SwitchTopMain [info] [0.340] // COMPILING < (class HyperCell.SwitchTop)>(9) [error] switchTop.scala:28: := not…
Jayant Bedwal
  • 1
0
votes
1 answer

Chisel Programming Error

I am having a problem in my Chisel code, I tried the following approach deqReg := Cat((0 until ports).map(ownReg === Cat(io.configVal(portBits*(_) + 2),io.configVal(portBits*(_)+ 1), io.configVal(portBits*(_))))) but I am getting the…
Jayant Bedwal
  • 1
0
votes
1 answer

Output of arbiter not stable

I have just found out this problem. Suppose I use a Arbiter to arbitrate the output of a bus driver from multiple parallel transaction initiators. The bus and initiators use DecoupledIO. It is known that Arbiter prioritizes in(0) over in(1).…
Wei Song
  • 545
  • 3
  • 11
0
votes
2 answers

Clock configuration for ShiftRegister in ChiselUtil

ShiftRegister is a usefull function to synchronize external signal with the main clock with two flip-flop : sync_signal := ShiftRegister(ext_signal, 2) That work well in this case. But is there a way to use it with an other clock like this :…
FabienM
  • 3,421
  • 23
  • 45
0
votes
1 answer

How to test the verilog module generated by Chisel in VCS ? How does vpi_uer.cc work in chisel?

In chisel-tutorial ,after I ran sbt "run Hello --backend v --compile --test --genHarness --vcd" I got the Hello.v ,Hello-harness.v ,vpi_user.cc files How can I test the Hello.v file? What is the usage of vpi_user.cc?
user5060279
  • 1
0
votes
1 answer

Adding uncore package to a Chisel project

There is a file rocc.scala in rocket repo which describes rocc interface, I want to build its verilog code and see the code. My problem is that I don't know how I can import other packages to my project such as "uncore." or "Util." and run…
Moriss
  • 325
  • 2
  • 12
0
votes
1 answer

How can generate the 32-bit RISCV form chisel soure. What are the required modifications?

According to the RISCV toolchain, we are generating the verilog files for Rocketchip as 64-bit. but we need 32-bit RISCV rocket chip. For that what are requirements and modifications in scala and chisel files. Is it possible to generate the 32-bit…
Santhosh Kumar
  • 25
  • 1
  • 3
  • 8
0
votes
1 answer

Chisel tools installation; Unable to fint scct

I am trying to get started with Chisel. Following the instructions on Chisel web page, I installed scala 2.11 and sbt, copied the build.sbt and Hello World example. However, I am unable to run the example. I am getting following…
Tariq Afzal
  • 1
0
votes
4 answers

clk event in chisel/scala

Some time ago I wrote a vhdl code for a description of a D-type flip-flop. A piece of code was: if (clk'event and clk='1') then q <= d; end if; How can I implement the following condition clk'event in scala/chisel language?
user3464253
  • 71
  • 1
  • 2
0
votes
1 answer

Inspecting or visualizing the graph of Chisel nodes

I'd like to use Chisel to generate circuits from trees of if-then statements that I have in an XML format (PMML decision trees). Simple splits like class Mod extends Module { val io = new Bundle { val x1 = UInt(INPUT, 8) val x2 =…
Jim Pivarski
  • 5,568
  • 2
  • 35
  • 47
0
votes
1 answer

Pass arg to testbench during runtime

I am rather new to CHISEL. Is it possible for CHISEL testbench to receive an arg passed in during runtime? For example, sbt run --backend c --compile --test --genHarness --dut1 --dut1 is meant to be received by the testbench as an arg. It will be…
David Chong
  • 45
  • 1
  • 3
0
votes
2 answers

What does UInt(0) mean?

I read that UInt(1) refers to a 1-bit decimal literal. I'm confused about what UInt(0) could mean. It is used in a Counter code that goes as follows :- package TutorialSolutions import Chisel._ object Counter {` `def wrapAround(n:…
chiselwood
  • 1
  • 2
1 2 3
…
45
46