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Questions tagged [chisel]

Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.

Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.

Features

  • Hardware construction language (not C to Gates)
  • Embedded in the Scala programming language
  • Algebraic construction and wiring
  • Abstract data types and interfaces
  • Bulk connections
  • Hierarchical + object oriented + functional construction
  • Highly parameterizable using meta-programming in Scala
  • Supports layering of domain specific languages
  • Sizable standard library including floating-point units
  • Multiple clock domains
  • Generates low-level Verilog designed to pass on to standard ASIC or FPGA tools
  • Open source on GitHub with modified BSD license
  • Complete set of docs
  • Growing community of adopters

Resources

680 questions
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Inner product (Dot product .) between two signal 4 bits using Chisel3

I'm a fresher in using Chisel3 to build the hardware components. Now, I'm trying to make a small module in which there are 2 inputs (vector A and vector B) and 1 outputs (out with 1 bits Unsigned Integer). Out is a Dot Product of A and B. I declared…
nhvlong06
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How to initialize a Reg of Bundle in Chisel?

I declared a Bundle for my specific data : class RValue (val cSize: Int = 16) extends Bundle { val rvalue = Output(UInt(cSize.W)) val er = Output(UInt((cSize/2).W)) val part = Output(Bool()) /* set if value is partial */ } And I want to…
FabienM
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How to understand this line of chisel code

I'm in the process of learning chisel and scala language and try to analyse some lines of rocket-chip code.Could anyone try to explain me this line?…
nemanja
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Developer's guide for Chisel?

Basically I would like to start hacking on the internals of Chisel/FIRRTL. It would help if someone could point me to where I could start looking at. I have been reading through the source code. I so far understand that Chisel has been implemented…
Anmol Sahoo
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Use FIRRTL Annotations to connect multi-bit wires and pins

I am writing down some firrtl transforms and I am using annotations to connect pins and wires, like : val named = ComponentName(inputWire.name, ModuleName(mod.name, CircuitName(top))) val anno = Traversable(SinkAnnotation(named, pinName)) The…
maku lulaj
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Expression _GEN_7 is used as a FEMALE but can only be used as a MALE

I am trying to write a Scala transform for firrtl, and at some point , I have a bunch of wires which should be connected to the input port. Because the number of wires could be to high, I dont want to connect each wire with a port, but concatenate…
maku lulaj
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How to extract a standalone FPU module from Rocket-Chip Chisel code?

I am working on Rocket Chip Generator, which is a SoC written in Chisel. My objective is to extract the Floating-Point Unit, in order to synthesize it and study its power consumption/area ...etc. separately from the rest of the SoC. So I cloned the…
noureddine-as
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Why does implicit type conversion from Int to UInt not work?

I'm trying to learn chisel3, and I also try to be able to use implicit type conversion from Int to UInt in specific case. Following is my code. package VecTest import chisel3._ import scala.language.implicitConversions object VecTestMain extends…
Mizunashi
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How to import getVerilog() function from the bootcamp examples?

I am not sure I understand how to use the getVerilog function from: https://github.com/freechipsproject/chisel-bootcamp/blob/master/2.1_first_module.ipynb [error] passthrough_test.scala:18:11: not found: value getVerilog [error] …
caylus
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What is the meaning of :*= and :=* operators?

I see some examples in the RocketChip, but could not find info in the API reference masterNode :=* tlOtherMastersNode DisableMonitors { implicit p => tlSlaveXbar.node :*= slaveNode }
Tampler
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How to add a sbus master to rocket-chip periphery

I'm trying to implement a DMA like periphery to the rocket chip. Meaning a module that is hooked to the pbus, and controlled by registers. it also has a master hooked to the sbus. I followed the sifive format to attach registers controlled…
user3567895
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What is the <> operator in Chisel?

The Chisel tutorials make use of what appears to be a <> operator, which is completely unfamiliar to me. What does it do? Also, where does it come from? Is there a conventional meaning for this operator in other Scala libraries or even other…
alcorn
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How to perform gate level simulation in Chisel3?

I wrote a hardware design in Chisel3 and also wrote a testbench in Chisel3 to test the design. And then, I synthesized the Verilog code which is generated by Chisel with Design Compiler. I want to verify that the behavior of RTL and Gate-Level are…
lssinee
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Can't printf with PeekPokeTester in Chisel3

I'm trying to print some value when testing my chisel3 design with this testbench code : package taptempo import chisel3._ import chisel3.iotesters import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester} import…
FabienM
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Formal verification with Chisel

Is it possible to do formal verification with Chisel3 HDL language? If yes, is there an open-source software to do that ? I know that we can do verilog formal verification with Yosys, but with chisel ?
FabienM
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