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Questions tagged [chisel]

Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.

Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.

Features

  • Hardware construction language (not C to Gates)
  • Embedded in the Scala programming language
  • Algebraic construction and wiring
  • Abstract data types and interfaces
  • Bulk connections
  • Hierarchical + object oriented + functional construction
  • Highly parameterizable using meta-programming in Scala
  • Supports layering of domain specific languages
  • Sizable standard library including floating-point units
  • Multiple clock domains
  • Generates low-level Verilog designed to pass on to standard ASIC or FPGA tools
  • Open source on GitHub with modified BSD license
  • Complete set of docs
  • Growing community of adopters

Resources

680 questions
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firrtl.Driver is deprecated - but what should we use instead?

I've updated rocket-chip today and noticed that FIRRTL now says this: ------------------------------------------------------------------------------ Warning: firrtl.Driver is deprecated since 1.2! Please switch to…
jbaxter
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How to iterate through similar registers definition in Chisel (regmap)

I have some similar register definition, and I want to write under the regmap construct. My code currently looks like this: val regs = RegInit(Vec(Seq.fill(5)(0.U(32.W)))) regmap ( ... 0x30 -> Seq(RegField(32,regs(0),RegFieldDesc("reg0",""), 0x34…
user3567895
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Chisel/Firrtl Verilog backend proof of work

Is there some built in test or tools for formal verification of chisel or firrtl design vs generated verilog? On which concepts verilog backend is build? Is there any bugs in it?
SpaceCowboy max
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Simplest way to generate Verilog code from Chisel code

What is the simplest way to generate Verilog code from existing Chisel code? Would i have to create my own build file? For example from a standalone scala file (AND.scala) like the following one.. import Chisel._ class AND extends Module { val…
mtosch
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Chisel: mapping separate input and output ports to inout pin

I'm generating Verilog from Chisel 3 source code and mapping the Verilog's top module ports to FPGA pins by using an UCF file. I have a set of inout pins in my design (SDRAM data pins), which on the Chisel side have to be expressed as separate input…
Luís Marques
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Chisel 3 assignment to bit range

This seemed to work in Chisel 2, but doesn't work now: class TestX extends Module { val io = IO(new Bundle { val a = Output(UInt(width=2)) }) io.a(1, 0) := UInt(0) } Error: [module TestX] Expression T_4 is used as a FEMALE but…
Luís Marques
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How does a missing boolean operator still compile?

I have code like this: val pop: Bool = ( (fsm === Fsm.None && canPop) || (fsm === Fsm.Some && canPop && fooBar) (fsm === Fsm.Other && canPop && dragonFruit) || (fsm === Fsm.Mom && canPop)) fsm is a ChiselEnum based state machine and the…
nic
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Another subtype after a type bound in scala

class PEControl[T <: Data : Arithmetic](accType: T), this is a class definition from riscv-gemmini. The Data type is the basic data type in chisel, Arithmetic provides some arithmetic operation on Data, and abstract class Arithmetic[T <: Data]. What…
Phantom
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How do you split modules into individual files using ChiselStage?

I would like to split modules into files, like the old --split-modules flag used to do. Passing this flag to ChiselStage throws an error that this is deprecated, however I cannot find any documentation on what the supported arguments to ChiselStage…
Guy Hutchison
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Get an item in Seq using UInt

I'm trying to write a cache memory, so I created a Seq of type Mem because I'm trying to have access to all elements in a set of the cache at the same time. val metaMem = Seq.fill(nWays) (Mem((nSets), new MetaData)) and then I want to have indexing…
Ali Sed
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Chisel3: Vec indexWhere expected Bool, actual Any

In Chisel, I have a Vec of Bools coming into a module. I would like to know the index of the first False which occurs. To obtain this, I tried to use the following: val faultIndex = Wire(UInt) faultIndex := comparison.indexWhere(x:Bool => x ===…
Parsen49
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Functional for loop in Scala/Chisel

I'm trying to find functional equivalent of the following algorithm (not really Scala or Chisel syntax): val x = Wire(Vec(n, UInt(L.W))) val z = Wire(UInt(L.W)) var y = 0; for (i <- 0 to (L-1)) { y = 0; for (j <- 0 to (n-1)) { y = y ||…
ubaabd
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Taking log2Ceil of UInt

I'm taking log2 of following calculation: tl_out.a.bits.size := log2Ceil(s1_row * s2_column * 4.U) where, s1_row and s2_column are UInt. I'm getting following error: [info] Compiling 1 Scala source to ...rocket-chip/target/scala-2.12/classes…
Sanket Khandare
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how to suggest name inside bundle in chisel3.2?

I'm using the suggestName API for IO(), for example class TestModule extends MultiIOModule{ val AXI = IO(new AXIWriteIO(32,32,4)).suggestName("axi") val S_AXI = IO(Flipped(new AXIWriteIO(32,32,4))) AXI.AW.suggestName("aw") AXI <>…
Hoohoo
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how to override/extend chisel signal naming

It seems not an easy thing to do or even impossible, but we are using a naming convention that prefix or postfix signals with "i_" or "o_" for inputs/outputs in verilog. Is there some method to mess with or override inside the chisel library to to…
Hoohoo
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