Can chisel print time like verilog

Question

In digital circuit simulation verification, time is a very important parameter. Verilog can use the $time function to obtain simulation time. I want to know if chisel has the same function.

Answer 1

I do not believe that Chisel has this functionality. However if there is something you need to use this for inside of a design, you can always create a Chisel BlackBox and include the $time print in that.

Chisel generally only prints synthesizable Verilog. That being said, it's possible someone has a library that includes this and can extend the print through a FIRRTL transform.