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I was studying the ways to make an efficient FPGA project (toward to become an ASIC design) which include division operations of simple 32 bits binary numbers.

I have found that the most expedite way to do it, is using LUT (Look-up table), than generating a complex division logic. That's fine, however, when I think about ASIC I imagine a physical microchip, with digital logic inside, I can't imagine to put a whole table inside to produce the division. I can understand it makes sense in an FPGA because it has a lot of resources including on-chip memory etc, but not on a definitive ASIC.

My question is, LUT is actually synthesizable in an ASIC design? Is this how chips which need division operation, are in fact made?

Also, LUT does consumes less area than creating a division module??

I am quite noob on this, I thank you for your input.

sujeto1
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2 Answers2

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General integer division is made using an iterative process, where each iteration generates a number of result bits based on either subtraction or table lookup, similar to when you did division on paper back in school. Specific integer division, for example if the numbers have few digits then a lookup table may be used instead, or if the divisor is an 2 ^ n number, then simple shifting may be used maybe combined with addition for rounding. So actual implementation of division actually depends on the arguments, and speed/size requirements.

Regarding your FPGA to ASIC conversion, then the LUTs in the FPGA is just a flexible way to implement general purpose combinational circuits, since an e.g. 4-input LUT can implement all outputs for a 4-input function. When you synthesize logical expressions to an FPGA, then the result will be a LUT representation since that is the building blocks available in an FPGA, but if you synthesize logical expressions to an ASIC, then the result will usually be a discrete gate representation since that is the building blocks available in an ASIC. The ASIC implementation is smaller and faster (for same technology), since the general purpose LUT overhead is avoided, however at the loss of the FPGA flexibility.

Morten Zilmer
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  • So in conclusion, LUT is feasible in ASIC and it's a practical option when designing a chip, right? – sujeto1 Nov 11 '16 at 05:30
  • LUT just means LookUp Table, and not a special primitive, but can be implemented in many ways both in ASIC and FPGA. Note that the FPGA technology is usually described using the concept LUT, which is then used to implement arbitrary n-input functions. An straight forward implementation of a LUT can be a RAM or ROM, or where the ROM functionality can also be implemented using hardwired gates. – Morten Zilmer Nov 11 '16 at 09:03
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Synthesis become popular in FPGA designers. Everything you need to know about LUT based architecture is a transistor level design techniques which required set of skills.

I personally go with verilog netlist file with netgen command. You can go FPGA - LUT Architecture Optmization

eInfochips - Komal C
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