0

Which of these hinders the simulation performance in my testbench and why (Looking for an answer from system verilog compiler perspective): 

task A;
wait(dut_if.a==1);
.
.
endtask

OR 

task A;
  forever @(posedge clk) begin 
    if(dut_if.a==1).. 
  end
endtask

PS: "a" is a dut signal which gets asserted at some clock edge during the simulation. Assume this task is called just once.

Omkar Manjunath
  • 13
  • 4
  • Thanks for your comments. So from what i understand, forever and always block once converted to low level language will be actually some kind of interrupt service routine and wait statements will be some thing like a branching instruction. Correct me if I'm wrong. It would be great if you could point me to some source which talks about system verilog from compiler perspective. – Omkar Manjunath Apr 13 '16 at 22:01

4 Answers4

4

The two aren't functionally equivalent. The first snippet waits until a goes high (i.e. that exact same cycle), whereas the second snippet waits until a is "seen" to be high at the clock cycle:

       _   _   _   _   _
clk  _| |_| |_| |_| |_| |_
            ______________
a    ______|

           |  |
           1  2

The numbers show you when each gets triggered. What you really want is:

@(posedge clk iff dut_if.a);

This is semantically equivalent to snippet 2. The comments @Coverify made should apply here as well (faster because no context switches).

Tudor Timi
  • 7,453
  • 1
  • 24
  • 53
2

The 1st option would have better performance. I am assuming that in the context of your usage, both the options are functionally correct.

The second piece of code, waits on every clock and then checks for the condition. Since the wait is inside forever loop, this code would result in context switching on every posedge of clk. On the other hand, the code in option 1 switches the context only once.

Puneet Goel
  • 858
  • 5
  • 8
0

Both options are not functionally equivalant.

But in this case, 2nd option would be better than 1st option, in simulation performance.

Because, in 1st option, tool needs to check the value of a, on each and every timestep, whereas, in 2nd option, tool will check only on posedge, not each timestep.

Karan Shah
  • 1,912
  • 1
  • 29
  • 42
0

Which has better performance? It depends on the simulator's implementation. In a true event base simulator, case 1 would have better performance because the evaluation code is not wake up on every clock edge. However, I suspect case 2 would have better performance in real world since the evaluation code is well aligned with the clock tick.

If your code is not modeling async logic, I recommend you stick with case 2. The code is easier to follow and understand. Align everything with the clock makes your life a lot easier.

hevangel
  • 95
  • 5