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I have been using TSMC 180nm Standard Cell Library before and here is its directory structure：

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In the directory of synopsys, things are as followers:

enter image description here

The file slow.db is used to synthesize the RTL Verilog in Design Compiler.

Now,I got a TSMC 65nm Standard Cell Library with similar directory structure to TSMC 180nm Standard Cell Library:

enter image description here

But in the directory synopsys,there is no db files but just a README file:

This package contains no timing models. The timing models for this library are in separate *.tgz files whose name starts with "ft" and has an identical process, library and release name as the name of this tgz file.

My question is how could i get the db file like "slow.db" in TSMC 180nm Standard Cell Library?

Thanks！

Paebbels
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chaotetung
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1 Answers1

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You have to find the *.tgz file (Which is a Gnu-Tarred-Compressed file) and unpack it.

Note that TSMC, UMC, SMIC and the like are very protective about their IP and often provide "get acquaintanced packages" which lets you play with their libraries, but not do in-depth design. As such they may not have provided you with all the design sources required.

Especially the physical cell library will only be released after you transfer a significant amount of money.

Oldfart
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