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I am eager to know if there is any real world application which includes following scenario:

Megabytes of continuous write-only to DRAM simultaneously from all (three or more) A53 cores (or any other Arm cores) – throughout the application as the only operation from the core.

The reason why I am asking is, I came accross a specific scenario while designing a chip in which the above operation is misbehaving, so would like to explore how to handle this specific scenario if it's valid.

I could think of only DRAM initialisation.

Nee
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  • It sounds kind of like a naive multithreaded Sieve of Eratosthenes algorithm that I think many people have tried. You have a big array of bytes initialized to 1. Thread #1 zeros out every multiple of 2 (except 2 itself), Thread #2 zeroes every multiple of 3, Thread #3 zeroes every multiple of 5, and so on. Each thread only writes, and when you get done, only the primes are left set to 1. It has terrible performance, so maybe not "real world", but it's at least something that people might realistically try. – Nate Eldredge Jan 25 '21 at 19:13
  • It is often difficult to get write only to dram, you would need the cache off and an way to write through/direct at the full width of the dram interface. some controllers can I assume. and the program would need to be not running out of dram. so yes dram init. at the same time if you are running something that in various possible ways is fetching from the cache and the only thing going out is data writes would again have to be some sort of write through that does no reads, so very hardware specific...(as in possibly nothing to do with the arm logic) – old_timer Jan 25 '21 at 20:05

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