Error: /..integrator.vhd(47): near "process": (vcom-1576) expecting IF VHDL

Question

I'm trying to add two registers storing signed bits one of 3-bit[FRQ(2 downto 0)] and other is 7-bit[PHS(6 downto 0)]...and has to store the addition of these two registers in 7-bit register [PHS(6 downto 0)]. Thanks in advance for your helpful gesture.

the error I get is..>>> Error: /..integrator.vhd(47): near "process": (vcom-1576) expecting IF VHDL

here is my code:

    library IEEE;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    --use ieee.std_logic_unsigned.all;


    entity integ is
        port (
            SMP_CLK : in std_logic;
            RESET : in std_logic;
            PHS : out signed (6 downto 0);
            FRQ : in signed (2 downto 0)
              );
    end integ;

    architecture behaviour of integ is

    signal sig_FRQ   : signed(2 downto 0) := (others => '0');
    signal ext_FRQ   : signed(6 downto 0) := (others => '0');
    signal sig_PHS   : signed(6 downto 0) := (others => '0');
    signal temp_PHS   : signed(6 downto 0) := (others => '0');

    begin 

    sig_FRQ <=FRQ;
    temp_PHS <= sig_PHS;
    --PHS <=signal_PHS;
    process (SMP_CLK, RESET)
    begin

    if sig_FRQ(2)='1' then
        ext_FRQ(6 downto 3) <= b"0000";
    else 
        ext_FRQ(6 downto 3) <= b"1111";
    --end if;

    if RESET='1' then
       sig_PHS <= b"0000000";


    elsif (rising_edge(SMP_CLK) ) then
    --  temp_PHS <= sig_PHS;
           sig_PHS <= signed(ext_FRQ) + signed(temp_PHS);



end process;


sig_PHS => PHS;

end behaviour;

Roman · Accepted Answer · 2017-04-17T15:44:39.210

2

You have some mess with if-elsif-else statement. After the line with ext_FRQ(6 downto 3) <= b"1111"; you have commented --end if; if you want to continue if-elsif-else statement next condition should start with elsif word rather than simple if as in your code.

And you need to close the if-elsif-else construction in the end.

As well as you need to add to sensitivity list sig_FRQ signal because you use it in comparison, if you don't add it to sensitivity list the following construction

if sig_FRQ(2)='1' then
    ext_FRQ(6 downto 3) <= b"0000";
else 
    ext_FRQ(6 downto 3) <= b"1111";
end if;

will work wrong.

In your case I suppose right version of the if-elsif-else constructions looks like:

process (sig_FRQ)
begin
    if sig_FRQ(2)='1' then
        ext_FRQ(6 downto 3) <= b"0000";
    else 
        ext_FRQ(6 downto 3) <= b"1111";
    end if;
end process;

process (SMP_CLK, RESET)
    if RESET='1' then
        sig_PHS <= b"0000000";
    elsif (rising_edge(SMP_CLK)) then
        --temp_PHS <= sig_PHS;
        sig_PHS <= ext_FRQ + temp_PHS;
    end if;
end process;

In the end, if you would like to assign result to output, you need to use another operator

PHS <= sig_PHS;.

edited Apr 17 '17 at 15:44

answered Apr 17 '17 at 09:06

Roman

375
2
7

I have to modify output port assignment but your suggestion was a lot helpful. Thanks a lot. Code is running now, although it need some rectification for proper addition. Since, after simulating it, I didn't got result as I expected. Anyhow, Thanks Again.!! – Gaurav Singh Apr 17 '17 at 09:30
Got it working as expected.!! Anyhow, I am implementing a FSM for data communication, to be used in modulation schemes using digital design. – Gaurav Singh Apr 17 '17 at 11:06
Ok, I was glad to help you anyway – Roman Apr 17 '17 at 11:12
I don't think it is a good idea to put both assignments in one process. `ext_FRQ`=combinatorial and `sig_PHS`=clocked... Also, `ext_FRQ` and `temp_PHS` are already signed. – JHBonarius Apr 17 '17 at 15:36
@J.H.Bonarius ok, I fixed my answer, thanks for your advice – Roman Apr 17 '17 at 15:46
In case of `RESET='1'` how should I assign all my signals to zero ?? Should I considered all signals used either in combinational or sequential logic or should I focus on sequential only? – Gaurav Singh Apr 19 '17 at 11:59
@Gaurav Singh add `RESET` to each sensitivity list of the process when you want to use it. In this case you will get asynchronous reset – Roman Apr 19 '17 at 14:33

Error: /..integrator.vhd(47): near "process": (vcom-1576) expecting IF VHDL

1 Answers1