Suppose I have variable length string as below:
Write <Address> <Data0> <Data1> <Data2>
Read <Address>
Write <Address> <Data0>
Write <Address> <Data0> <Data1> <Data2> <Data3>
How do I read in SystemVerilog or Verilog using file operations. I know to read when there is fixed length of text
integer file = $fopen(file_name,"r");
code = $fgets(line, file);
code = $sscanf(line, "%s %h %h %h", txn_type, Address, Data[i]);