I am facing the "Size mismatch error" in verilog

Question

parameter N1 = 5;
parameter N2 = 5;
wire [(N1+N2-1):0] seckey [8:1];    
shiftreg #(.depth(N1+N2-1)) sr1( .clk(clk), .reset(reset), .data_in(muxout[1]), .data_out(seckey[0]));

//--------------------------------------------------------------------------//

module shiftreg(
input clk,
input reset,
input data_in,
output data_out
);

parameter depth = 9;
wire [depth:0] connect_wire;
wire [depth:0] data_out;
//wire [depth:0] data_out;
assign connect_wire[0] = data_in;

assign data_out[depth:0] = connect_wire[depth:0];

genvar i;
generate
    for(i=1; i<=depth; i=i+1) begin: loop1
        ff dff(.d(connect_wire[i-1]), .clk(clk), .reset(reset), .q(connect_wire[i]));
    end
endgenerate

endmodule

//--------------------------------------------------------------------//

module ff(
input d,
input clk,
input reset,
output reg q
);



always @ (posedge clk or posedge reset)
begin
    if (reset) begin
    q <= 1'b0;
    end
    else begin
    q <= d;
    end
end


endmodule

//------------------------------------------------------------------------//

Value of N1 and N2 is 5. I am getting the error "Size mismatch in connection of port (data_out). Formal port size is 10-bit while actual signal size is 1-bit"

I have set the size of the data_out port to be 10 bits but its still showing the signal size to be 1 bit.

score 1 · Answer 1 · answered Feb 03 '18 at 23:33

To set the size of data_out, you need to set the size where you declare the parameter. Try the header below

module shiftreg(clk, reset, data_in, data_out);

parameter depth = 9;
input clk;
input reset;
input data_in;
input [depth:0] data_out;

Also:

assign data_out[depth:0] = connect_wire[depth:0];

can be replaced with

assign data_out = connect_wire;

I am facing the "Size mismatch error" in verilog

1 Answers1