How to flatten Verilog bus to individual wires using Yosys

Question

Simple question here. Is there a method in Yosys to flatten arrays? i.e.:

wire [1:0] rdata; becomes wire rdata_1; wire rdata_0;

Answer 1

Here's my answer. Not sure when it should be called. After proc seems to work.

proc
opt
splicenets -format __ # <---
[..]