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I want to synthesis a vhdl design for ASIC standard cell libraries to find the circuits area requirement. How can i do it for for Virtual Silicon (VST) standard cell library UMCL18G212T3 or UMC L180 0.18µm using Yosys? Does Yosys support vhdl code or do i need to write it in verilog?

crypt
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  • [VHDL Frontend Efforts](https://github.com/YosysHQ/yosys/wiki/VHDL-frontend-efforts). GHDL-synth: [https://github.com/tgingold/ghdlsynth-beta](https://github.com/tgingold/ghdlsynth-beta) Requires a minor patch to the yosys Makefile. Most of the heavy lifting is actually done in [https://github.com/ghdl/ghdl/tree/master/src/synth](https://github.com/ghdl/ghdl/tree/master/src/synth). –  May 29 '19 at 18:44
  • how to map it to a virtual silicon library? – crypt May 29 '19 at 18:53
  • Do you have the VHDL source? –  May 29 '19 at 18:54
  • Real silicon libraries are expensive. Fork out a $100.000 and get the library from the vendor. – Oldfart May 29 '19 at 18:57
  • actually i dont need to fabricate an IC. Yes i have the implementation, i need to map it to any free standard cell library to see area requirements. does not matter which library. its just an acadamic exercise – crypt May 29 '19 at 18:59
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    VHDL - no, forget about it. Use Verilog, just like the rest of the industry does. As for the rest, see http://opencircuitdesign.com/qflow/ – SK-logic May 31 '19 at 14:34
  • @SK-logic what about the standard cell libraries, are there free open source standard cell libraries? – crypt May 31 '19 at 18:31
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    Yes, OSU cell libraries are open source and come with QFlow. I guess they should be sufficient for your purpose. – SK-logic May 31 '19 at 21:58

1 Answers1

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Via the Yosys webpage. It looks like only Verilog.

About

Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. Selected features and typical applications:

Also from the same page...

Example Usage

Yosys is controlled using synthesis scripts. For example, the following Yosys synthesis script reads a design (with the top module mytop) from the verilog file mydesign.v, synthesizes it to a gate-level netlist using the cell library in the Liberty file mycells.lib and writes the synthesized results as Verilog netlist to synth.v:

> # read design  read_verilog mydesign.v
> 
> # elaborate design hierarchy hierarchy -check -top mytop
> 
> # the high-level stuff proc; opt; fsm; opt; memory; opt
> 
> # mapping to internal cell library techmap; opt
> 
> # mapping flip-flops to mycells.lib dfflibmap -liberty mycells.lib
> 
> # mapping logic to mycells.lib abc -liberty mycells.lib
> 
> # cleanup clean
> 
> # write synthesized design write_verilog synth.v
Tropical_Peach
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