Questions tagged [xilinx]

Xilinx is a major brand of Field Programmable Gate Arrays (FPGA) and CPLDs (Complex Programmable Logic Devices)

Xilinx is known for its fpga devices:

Spartan
Virtex
Kintex
Artix
Zynq Portfolio: System on Chip device along with a FPGA
Versal: 7nm adaptive compute acceleration platform (ACAP)

And the software tools it offers:

Vivado HLS: IP creation using C, C++ and System C
Vivado IP Integrator: create, configure and integrate IPs
System Generator: define, implement and test DSP algorithms
Vitis: embedded software and accelerated applications development
Vitis AI: AI inference stack to run neural networks

With intellectual properties like microblaze soft processor.

Useful links

Website: https://www.xilinx.com
Knowledge base: https://www.xilinx.com/support.html#knowledgebase
Documentation: https://www.xilinx.com/support.html#documentation
Forum: https://forums.xilinx.com
Versal info.

1399 questions

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2 answers

how does inout parameters be implemented?

I know what the inout parameters is and how to use them. Assume that we have an inout parameter io and want to create a bidirectional static RAM such as the following code : LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY sram IS port( …

vhdl fpga xilinx

asked Jan 02 '15 at 09:21

Amir

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1 answer

How can I make a FPGA prototype with a touch-screen display?

I'm looking to make an FPGA (or similar) physical prototype, but including a small touch screen display. (Picture a 2" or similar touch screen display. For example, imagine say some sort of small battery-powered toy with a small touch screen…

touchscreen xilinx prototyping

asked Apr 23 '14 at 16:34

Fattie

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1 answer

VHDL/PlanAhead Error: remains a black-box since it has no binding entity

How can this error be fixed? PlanAhead 14.7 is able to synthesize but not simulate correctly for this simple counter. The instance "dut : countr port map" remains with a red question mark in the sources tab. I've made sure that all signals are…

vhdl simulation xilinx

asked Apr 15 '14 at 11:42

chilipepper

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0 answers

Can't connect to wifi with recommended Edimax EW7811U

I can connect via ethernet, but have been trying to setup wifi using the recommended Edimax EW7811U, as mentioned here: https://redpitaya.zendesk.com/hc/en-us/articles/200295492-WIFI-connection I have a Raspberry Pi sitting right next to it,…

linux raspberry-pi wireless xilinx redpitaya

asked Mar 05 '14 at 03:48

Branton Davis

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1 answer

HOW do I write from a Spartan6 to the Micron external Cellular RAM on the Nexys3 FPGA Board?

I have looked everywhere, the datasheet, the Xilinx website, digilent, etc. etc. and can't find anything! I was able to use the Adept tool to verify that my Cellular RAM is functioning correctly, but I just can't find any stock VHDL code as a…

vhdl ram fpga xilinx

asked Sep 17 '13 at 21:59

LuckyLuc

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2 answers

How to deduce from synthesis report

I had coded the 80c51 architecture in VHDL using xilinx. In an attempt to increase the clock frequency, I had pipelined all the 80c51 instructions. The instructions were able to execute as desired, for eg. when the 1st instruction is being…

vhdl xilinx

asked Nov 13 '12 at 06:12

Ice

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1 answer

Flip-Flop triggered on the edge of two signals

I need a flip flop that reacts on the edges of two different signals. Something like this: if(rising_edge(sig1)) then bit <= '0'; elsif(rising_edge(sig2)) then bit <= '1'; end if; Does such a flip flop exist or is there some other technique…

vhdl xilinx virtex

asked Aug 19 '09 at 18:08

giroy

2,203
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27
38

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1 answer

VHDL/Verilog: access HDMI port

I just got a new board. http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,836&Prod=ATLYS As you can see, I have two HDMI inputs and two HDMI outputs on the board. What I want to do is take one HDMI input and perform some transforms on the…

vhdl verilog fpga xilinx hdmi

asked Oct 07 '12 at 15:43

Eamorr

9,872
34
125
209

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2 answers

BRAM_INIT in VHDL

I am simulating a processor based design where the program memory contents are held in a BRAM. I am realizing the program memory using VHDL (inferring BRAMs). I am trying to avoid CoreGen because I want to keep the design portable. Eventually this…

embedded vhdl fpga xilinx

asked May 11 '12 at 17:08

boffin

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2 answers

How to determine how many slices a design uses

I've implemented a 16-bit ALU and a register file in VHDL using the Xilinx ISE. I've been asked how many slices my design uses, and I have no idea how to go about answering that question. I'm not working with a particular chip or simulating one, I…

vhdl fpga xilinx

asked Oct 10 '11 at 18:35

ZacAttack

2,005
5
21
34

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2 answers

Implementing hardware that divides an 8 bit number by 3 (11) in binary

I want to create a schematic that divides any 8-bit number by 3, on a Xilinx device in case that matters. For example, hardware takes two inputs (111101) and (11) and returns the division of two numbers which is 010100. I don't need to worry about…

assembly xilinx integer-division xilinx-ise hardware

asked May 09 '22 at 13:18

user19076994

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1 answer

How to provide the U-Boot default environment from a file in Yocto?

I want to avoid setting the default environment in CONFIG_EXTRA_ENV_SETTINGS, therefore I've set CONFIG_DEFAULT_ENV_FILE="uEnv.txt" and created that text file but bitbake doesn't find it: make[1]: *** No rule to make target 'uEnv.txt', needed by…

yocto xilinx bitbake u-boot

asked Oct 15 '21 at 16:00

Silvio Ankermann

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1 answer

Xilinx ISE fails to use std_logic_1164

I have Xilinx ISE 13.1 installed on an ACER laptop with Win7 (64bit). After installing the software (WebPACK version) I created an empty VHDL module and ran "check syntax". The process failed with the following errors: Error:HDLParsers:3016 -…

std vhdl xilinx

asked Jul 27 '11 at 07:43

Edgar Roex

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1 answer

Microblaze & C++ | Why does the code size increase dramatically under certain conditions?

I have been developing embedded software for the Microblaze processor for more than a year using C++. My designs were not so complex, so I wasn't using the powerful, object-oriented features of the language. For a while, I have been trying to…

c++ embedded xilinx microblaze

asked Apr 15 '21 at 17:35

Caglayan DOKME

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4 answers

Nested if (rising_edge(clk)) statements in VHDL

so I’ve come across some old code that I have to replicate, but it won’t compile with the new Xilinx compiler, so I need to figure out exactly what it does. I have something like this: if rising_edge(clk) then —do some things if…

clock vhdl fpga xilinx

asked Jun 16 '11 at 16:51

Jamal

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