Questions tagged [xilinx]

Xilinx is a major brand of Field Programmable Gate Arrays (FPGA) and CPLDs (Complex Programmable Logic Devices)

Xilinx is known for its fpga devices:

Spartan
Virtex
Kintex
Artix
Zynq Portfolio: System on Chip device along with a FPGA
Versal: 7nm adaptive compute acceleration platform (ACAP)

And the software tools it offers:

Vivado HLS: IP creation using C, C++ and System C
Vivado IP Integrator: create, configure and integrate IPs
System Generator: define, implement and test DSP algorithms
Vitis: embedded software and accelerated applications development
Vitis AI: AI inference stack to run neural networks

With intellectual properties like microblaze soft processor.

Useful links

Website: https://www.xilinx.com
Knowledge base: https://www.xilinx.com/support.html#knowledgebase
Documentation: https://www.xilinx.com/support.html#documentation
Forum: https://forums.xilinx.com
Versal info.

1399 questions

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0 answers

How to enlarge bus width using Vitis libraries BLAS

I am trying to use the BLAS L1 implementation from Vitis libraries, I want to set bus width to 128 bit, I am doing it using the ap_int.h header, defining an ap_int<128> structure. I implemented an OpenCl kernel with VITIS HLS module, but the…

opencl xilinx blas vivado-hls

asked Jun 25 '20 at 08:45

joepol

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1 answer

Problems with inclusion of C header file with automatically generated makefile

I have started to develop the C language software in the Xilinx Vitis IDE which Eclipse based. Organization of my project is following: -Application -Drivers -drivers -Adc -Pwm -Pwm.c -Pwm.h -Utils -Bits.h -Maths.h All the directories…

c makefile xilinx xilinx-edk

asked Jun 11 '20 at 15:00

Steve

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1 answer

Matrix Multiplication of two Complex Vectors in Simulink

Two questions really, But I would like to make it more descriptive : I am implementing a Modulator which involves Matrix Multiplication of complex Vector: Just to give an example : cck_encoding_table(1,:)= [ 1j 1 1j -1 1j 1 -1j 1…

fpga simulink xilinx system-generator

asked May 09 '11 at 22:34

Kiran

8,034
36
110
176

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1 answer

What files to check into git in a Vivado Project file?

I have a vivado project directory that I want to check into git. I have all my VHDL source files one directory up from the "vivado project" directory under "../hdl/". My guess is that I only need to check in: git add ./hdl/*.vhd git add…

xilinx vivado

asked Aug 07 '19 at 16:20

pico

1,660
4
22
52

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2 answers

using values instead of pointers as function arguments

I have this function "cost_compare" that I would like to offload on FPGA for some experimental purposes. This function, how it is called and its arguments are as follows. The synthesis tool doesn't accept double pointers as arguments for HW…

c fpga xilinx synthesis

asked May 31 '19 at 01:33

Hooman

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1 answer

How can I force a cache flush for a process from a Linux device driver?

I'm working on a research project that requires me to perform a memory capture from custom hardware. I am working with a Zedboard SoC (dual-core ARM Cortex-A9 with FPGA fabric attached). I have designed a device driver that allows me to perform…

linux linux-device-driver xilinx zynq petalinux

asked Mar 21 '19 at 20:21

ngc6027

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1 answer

Vivado infers incorrect FREQ_HZ for AXI busses to my module

I'm working on a design in Vivado. My top level design is a block diagram. The block diagram has IP blocks and my Verilog RTL modules. Whenever I change my main module and Verilog updates the block diagram, it always incorrectly infers the clock…

verilog xilinx vivado zynq

asked Feb 26 '18 at 07:23

Ethan Reesor

2,090
1
23
40

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1 answer

Array indexes to wide for array

I have the following problem when accessing arrays in VHDL: Say I have an array which is not of size 2^n, for example of size 6. Then, if I want to access this array using an index of width 3 bits (=ceil(log2(6))), it is clear that this index can…

arrays indexing vhdl xilinx synthesis

asked Feb 03 '11 at 00:33

Klowse

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2 answers

Simple SR Latch Simulation in VHDL(with Xilinx) doesn't oscillate

I've learned that SR-Latch does oscillate when S and R are both '0' after they were just '1' in following circuit VHDL Code. here is VHDL of SRLATCH library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity SRLATCH_VHDL is port( S : in STD_LOGIC; …

vhdl xilinx

asked Oct 14 '17 at 15:03

Seung Jin Lee

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1 answer

what is the main difference between project mode and non project mode in vivado?

And when the synthesis is completed i am getting many files like .fw, .mcs, .prm along with .bit file, and can we dump those other files other than .bit file into FPGA? Which one is more advantageous project mode or non project mode? Coding is done…

verilog xilinx synthesis vivado

asked Oct 27 '16 at 03:52

vlsi_user

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1 answer

Copying ISim results as strings/text

I'm creating a VHDL project, and using ISim to simulate beforehand - which is all fine. However, my results use fixed point - and although Isim can represent its signals as a range of radix's, unsurprisingly, fixed point decimal isn't one of…

vhdl simulation fpga xilinx xilinx-ise

asked Mar 05 '16 at 18:11

davidhood2

1,367
17
47

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1 answer

Why do we use REG in FGPA / VHDL / VIVADO?

I am programming with Xilinx's vivado in verilog. I was wondering why for some outputs we use reg For example reg [3:0] encoder_output we use that because our 16 to 4 encoder has 4 outputs right? I am assuming that we use reg whenever we need to…

verilog xilinx vivado

asked Nov 02 '15 at 19:19

Kenny Truong

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1 answer

POSIX: how to perform a context switch between threads?

I want to implement the context switching between threads using Xilkernel, but there is no primitive POSIX-compliant that allows to stop and then resume the execution of a thread. Is there anyone who can help me?

linux-kernel posix fpga xilinx context-switching

asked Oct 19 '15 at 23:05

khaledrmse

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2 answers

Error synthesizing hierarchical names in vivado

Using Vivado 2015.1, I'm attempting to use a hierarchical name to access an object on the top level module of my design. The simulation runs fine but I receive the following synthesis error: [Synth 8-660] unable to resolve 'top'…

verilog fpga system-verilog xilinx vivado

asked Jun 25 '15 at 06:10

jwanga

4,166
4
26
27

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0 answers

PicoBlaze 8-bit Microcontroler jump and call instruction

I am a student and I have to create an PicoBlaze 8-bit Microcontroller based on this documentation XAPP213. I have a problem when I have to run a jump or call instruction: When I jump or call the next instruction I forced to be a NULL instruction…

vhdl xilinx picoblaze

asked May 06 '15 at 07:49

Tandura

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