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I've implemented a 16-bit ALU and a register file in VHDL using the Xilinx ISE. I've been asked how many slices my design uses, and I have no idea how to go about answering that question. I'm not working with a particular chip or simulating one, I just wrote the vhdl and debugged it by using a test bench.

Is there a way to get the ISE to generate how many slices my design uses? Or do I need to go through all my code and count up my operations? Or is it as simple as defining what type of components I used?

Nathan Farrington
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ZacAttack
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  • Have you considered checking out http://electronics.stackexchange.com? (I have no idea of your question would be better there or not, not my domain at all.) – Mat Oct 10 '11 at 18:40
  • That was helpful, but I still couldn't find what I was looking for. Thanks though! – ZacAttack Oct 10 '11 at 19:00
  • Ugh, I figured it out. The trick is to click whatever module you want to get the slice count for and set it as the top level module by going to Source->Set as top level module. Once you do that, under the Processes pane (making sure the module is still highlighted in the Sources pane) go to the Synthesize - XST and double click 'View Synthesis Report'. The number of slices for that module is then listed in that report. I'll post this as an answer in a bit (I don't have enough rep to answer my own question for a while). – ZacAttack Oct 10 '11 at 19:45
  • You should post that as an answer. It's fine to answer your own questions, you might even get some reputation from it :) – Mat Oct 10 '11 at 19:47
  • I will, I just need to wait 6 hours -_- – ZacAttack Oct 10 '11 at 20:03

2 Answers2

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To get a true view of what resources your design will consume use the map report. Implement the design and look at the hierarchical report of the usage (Slices, slice registers(or flip-flops), LUTS, LUTRAM, BRAM, DSPs, etc) of each module in your design in the map report file. In ISE 13.2 that is Section 13 of your _map.mrp file. You may have to enable the -detail switch in map.

Slices can be a deceptive metric (especially after a map report) since if you only use a single element of a slice it will count the entire slice as used. You will have to understand what is in a slice to really understand what the usage number means. Virtex 6 for example has 8 flip-flops and 4 6-input LUTS per slice.

If you only look at the synthesis numbers (slice flip-flops and slice LUTS) you may miss any netlist black boxes that your design uses (ie coregen elements, microblaze, system generator, or third party IP delivered in netlist form).

davidd
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  • In this case how should I view the slice count? I figured it would count a slice even if I used only a single component on it, so I figured I should view it as a 'worst case' sort of evaluation. But your saying that it discounts some elements. In that case, how is this metric even remotely helpful!? – ZacAttack Oct 12 '11 at 18:18
  • When you say slice count what is the text of the metric you are viewing? Does it say X slices or X slice Registers/LUTS. After synthesis and before implementation the tools really only know how many registers and how many LUTs are needed. It takes map and placement to determine how many slices will be needed for that number or registers and LUTs. Simply dividing by the number of LUTS/Registers per slice is usually not realistic. – davidd Oct 12 '11 at 20:40
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Ugh, I figured it out.

The trick is to click whatever module you want to get the slice count for and set it as the top level module by going to Source->Set as top level module. Once you do that, under the Processes pane (making sure the module is still highlighted in the Sources pane) go to the Synthesize - XST and double click 'View Synthesis Report'. The number of slices for that module is then listed in that report.

ZacAttack
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