Questions tagged [xilinx]

Xilinx is a major brand of Field Programmable Gate Arrays (FPGA) and CPLDs (Complex Programmable Logic Devices)

Xilinx is known for its fpga devices:

Spartan
Virtex
Kintex
Artix
Zynq Portfolio: System on Chip device along with a FPGA
Versal: 7nm adaptive compute acceleration platform (ACAP)

And the software tools it offers:

Vivado HLS: IP creation using C, C++ and System C
Vivado IP Integrator: create, configure and integrate IPs
System Generator: define, implement and test DSP algorithms
Vitis: embedded software and accelerated applications development
Vitis AI: AI inference stack to run neural networks

With intellectual properties like microblaze soft processor.

Useful links

Website: https://www.xilinx.com
Knowledge base: https://www.xilinx.com/support.html#knowledgebase
Documentation: https://www.xilinx.com/support.html#documentation
Forum: https://forums.xilinx.com
Versal info.

1399 questions

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1 answer

Serial communications with Digilent Atlys board

I have an Atlys board http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,836&Prod=ATLYS with Spartan6 FPGA on it. I want to setup serial port communications with host PC via onboard USB-UART bridge by EXAR. Everything's ok when running…

terminal serial-port fpga xilinx spartan

asked May 26 '11 at 15:56

Andrey Pesoshin

1,136
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1 answer

how to add python in xilinx vitis

I have implemented a Zynq ZCU102 board in vivado and I want to use final ".XSA" file into VITIS, but after creating a new platform, its languages are C and C++, While in the documentation was told that vitis supports python. My question is how can I…

python fpga xilinx

asked Feb 16 '20 at 04:54

SahaTib

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0 answers

confusion between u-boot.elf and u-boot

Installed Vivado 2018.2 Clone u-boot git clone https://github.com/Xilinx/u-boot-xlnx.git change directory to u-boot-xlnx source /opt/Xilinx/Vivado/2018.2/settings64.sh export CROSS_COMPILE=aarch64-linux-gnu- export ARCH=aarch64 make…

linux-kernel xilinx u-boot arm64

asked Feb 05 '20 at 14:26

coolicelee

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1 answer

Vivado: Warning The clock pin x_reg.C is not reached by a timing clock (TIMING-17)

I'm trying to compile some FPGA code using Xilinx's Vivado tool. However, when I run "Synthesis" and then select "Report methodology"...I get the following list of Bad Practices: TIMING-17 TIMING #1 Warning The clock pin last_anthony_reg.C is not…

vhdl fpga xilinx vivado

asked Aug 14 '19 at 19:30

pico

1,660
4
22
52

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2 answers

vivado block designer not updating RTL interface in block design after modifying verilog or vhdl RTL files

I would swear that vivado has a bug in that it never refreshes any interface changes made to an RTL file, verilog or vhdl, after it has been pasted into the "block design" with "add module".... What the secret to get Vivado block designer to see…

vhdl verilog fpga xilinx vivado

asked Jun 07 '19 at 17:40

pico

1,660
4
22
52

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3 answers

GHDL simulator doesn't support vhdl attributes without error?

I wrote some vivado RTL and then added some vhdl attributes to the ports of the entity to define the interface to Xilinx Vivado tool as follows: library ieee; use ieee.std_logic_1164.all; entity vivado_rtl_island is port( -- Clocks …

vhdl fpga xilinx vivado ghdl

asked Jun 04 '19 at 12:52

pico

1,660
4
22
52

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1 answer

Xilinx, Zynq, AXI4 interconnect. What are the performance implications of configuring register slice and data fifo options?

Consider an AXI4 Interconnect on the PL (FPGA) side. When I double click to see the available options, there is a tab in Slave interfaces. Containing the following options. What is the purpose of enabling register slice? Does outer refer to the…

xilinx vivado zynq axi4

asked Dec 26 '18 at 11:58

CJC

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2 answers

Is everything really a string in TCL?

And what is it, if it isn't? Everything I've read about TCL states that everything is just a string in it. There can be some other types and structures inside of an interpreter (for performance), but at TCL language level everything must behave just…

tcl xilinx vivado

asked Nov 28 '18 at 05:04

Anatol

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1 answer

VHDL - ror and rol operations

How can I solve this problem? reg variable is defined as: signal reg:STD_LOGIC_VECTOR(7 downto 0):="00000001"; There is a problem with ror operation in the code below. The error message is: Line 109: Syntax error near "ror". Line 108: found '0'…

syntax vhdl xilinx

asked Nov 20 '18 at 08:56

kaann45

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1 answer

Add kernel configuration options using configuration fragments in custom YOCTO layer

I am currently trying to modify the kernel configuration (overwrite default xilinx-linux layer configs) by adding configuration fragments to my custom layer like this : .bbappend file: FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}" SRC_URI =+…

linux-kernel yocto xilinx bitbake zynq

asked Apr 26 '18 at 09:55

Logen Sand

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1 answer

Running Ada on the Zynq using a Digilent Zybo development board

I've been successfully using Vivado and the SDK to develop VHDL and C for the Zynq XC7Z010 on a Digilent Zybo board. I've also been using the GNAT GPS IDE to learn Ada targeted to an STM32F4 processor (using one of the supported development…

ada xilinx zynq gnat-gps

asked Mar 19 '18 at 23:55

Max van Daalen

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1 answer

DISTRO 'poky' not found. Please set a valid DISTRO in your local.conf

New to Yocto. Trying to build an image for Xilinx Zynq. Followed instructions on https://github.com/Xilinx/meta-petalinux. Don't need everything there, so removed some of the layers. When I execute bitbake zynq-generic I get the following error: $…

xilinx yocto bitbake openembedded

asked Nov 02 '17 at 21:42

flashburn

4,180
7
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109

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1 answer

combine ports to bram interface

I want to write an IP to store/read data using BRAM. What I have so far is using the (C)DMA to read memory mapped data out of the RAM and get an AXIS. Then I created a new source file in VHDL to accept the AXIS on one side which worked like a…

vhdl xilinx vivado

asked Oct 13 '17 at 14:23

akira hinoshiro

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2 answers

Where to force xilinx ISE to use block-rams?

I synthesized a small device to test the block-ram inference. I got a message from XST : The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on…

vhdl fpga xilinx

asked Jan 12 '11 at 16:29

JCLL

5,379
5
44
64

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0 answers

Is it possible to open a Vivado project via Tcl and export it via write_project_tcl as Tcl?

Xilinx Vivado can export the content of a *.xpr file (Xilinx Vivado project file) as Tcl. Therefore a Tcl command exists in GUI mode (project mode): write_project_tcl {C:/.../project/KC705.tcl} From a version control perspective, it's better to…

git tcl xilinx vivado

asked Oct 12 '17 at 05:25

Paebbels

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