Questions tagged [vlsi]

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.

In addition, VLSI Technology, Inc was a company which designed and manufactured custom and semi-custom ICs. The company was based in Silicon Valley, with headquarters at 1109 McKay Drive in San Jose, California. Along with LSI Logic, VLSI Technology defined the leading edge of the application-specific integrated circuit (ASIC) business, which accelerated the push of powerful embedded systems into affordable products.

129 questions

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2 answers

What does shared memory do when they get 2 write request from 2 cores in RISC V multi core processor?

I'm just doing a project "design a dual-core processor based on RISC-V ISA no pipeline, no private or share cache and 2 cores are shared a data memory". I have designed RISC V single core processor and it's worked. There are something i don't…

asked Nov 25 '19 at 15:08

Nguyễn Phan Hoàng Phúc

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3 answers

Is it possible to have two instance have same name in the netlist?

Is it possible to have two flops/any other instances have the same name in the netlist? Considering that there is no hierarchy, say I have a design of 10M instances and there exists an flop called foo, is it possible that another flop have same name…

verilog system-verilog vlsi netlist

asked Feb 27 '19 at 06:16

Hemant Bhargava

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What book should I refer for flip flop timing diagram for VLSI (for such question given below)?

enter image description here I am pursuing masters in electronics system design and this was my question paper for today exam was unable to answers the first three questions properly.

clock digital flip-flop vlsi timing-diagram

asked Feb 19 '19 at 16:22

Varun

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1 answer

Can be a few supply1 nets in verilog code? If yes, what is the meaning?

module inst(); supply1 sp1; supply1 sp2; top…

verilog system-verilog vlsi

asked Jan 08 '19 at 14:02

karen.nik98

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1 answer

How do I communicate multiple ARINC429 channels with SPI slave device in VHDL

enter image description here I am developing an application of receiving Master data from CPU and transmiting to multiple channels through the SPI salve. How do I do memory map for SPI slaves for multiple channels How do I communicate multiple…

vhdl spi vlsi

asked Oct 08 '18 at 10:39

srihari

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2 answers

How to access sequence data from scoreboard

In my project, there are so many sequences which handle by virtual sequence. One of sequence has the information of dimensions of box size and start values. So I need to send sequence to scoreboard. I had tried by UVM ports At sequence: uvm_…

system-verilog uvm vlsi

asked Jun 13 '18 at 13:45

user9169344

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1 answer

10:1024 bit decoder in verilog

I tried to implement 10:1024 bit decoder in verilog with proper test bench using behavioural modeling. The Code is shown below. module decoder(input [9:0]address,output reg [1023:0]add); reg [9:0]i; always@(address) begin …

verilog decoder vlsi

asked Apr 24 '18 at 16:45

mohitesh07

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1 answer

Error compiling VHDL in VLSI

I am creating a CPU in my VLSI, starting with a register: library ieee; use ieee.std_logic_1164.all; package types is type BYTE is array (7 downto 0) of std_logic; end types; -- Have to use one file because of Electric's compiler library…

vhdl cpu vlsi

asked Dec 30 '17 at 17:57

Rdrpenguin

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1 answer

how to concatenate bit with a string in system verilog?

if(ci.busy) begin// writing **dataout** = {dataout,string'(**ci.dout**)}; $sformat( request,"%b",req.dout ); $fwrite(data, request); end here ci.dout is bit and dataout is string. This is the code I was using to convert bit to string…

verilog system-verilog vlsi

asked Nov 20 '17 at 21:28

Raviteja

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3 answers

Pulse counter in verilog

I am trying to build a pulse which is goes high for 8 pulses of clock and goes low for rest. So when enable and clock is high pulse goes high while after 8 pulses of clock pulse goes low. How can i implement and approach this in verilog. Here's what…

verilog hdl vlsi

asked Oct 04 '17 at 17:43

Kashish Jain

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1 answer

Propagational delay in circuits

which is better for accurate proportional delay: spice simulation method or calculation using elmores delay (RC delay modeling)

circuit vlsi asic

asked Aug 01 '17 at 10:01

Qurat

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3 answers

same source, different clk frequency(multi-clock design)

how to handle the multi-clock design signals with the clock generated from the same source? For example, one clock domain is 25Mhz the other one is 100Mhz how can I handle the data bus from 25Mhz to 100Mhz and also 100Mhz to 25Hhz? don't want to…

verilog system-verilog vlsi asic

asked Jun 09 '17 at 20:31

user2442045

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1 answer

SystemVerilog priority modifier usage

I'm reading about SV priority keyword. I found following example in on of the papers written by Sutherland: I'm not quite sure why we can see simulation synthesis mismatch if {priority} is NOT used. Lets assume we don't use {priority} and {IRQ} is…

verilog system-verilog digital-logic register-transfer-level vlsi

asked Apr 28 '17 at 20:32

newbie

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Data extraction from netlist line by line using perl

My question is regarding extraction of data from a file in Perl. In the attached file there is standard format of net list. After running the program I got the elements into an array @name_gate but when I tried to print @name_gate[0] instead of the…

perl vlsi netlist

asked Mar 27 '17 at 04:29

Blackwind

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1 answer

Associative array with wildcard in system verilog

Is it possible to iterate over an associative array with wildcard "*" using foreach loop?

verilog system-verilog vlsi

asked Feb 28 '17 at 10:07

Xeroxpop

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