10:1024 bit decoder in verilog

Question

I tried to implement 10:1024 bit decoder in verilog with proper test bench using behavioural modeling. The Code is shown below.

module decoder(input [9:0]address,output reg [1023:0]add);
    reg [9:0]i;
    always@(address) begin
        for(i=0;i<1024;i=i+1) begin
            add[i]=(address==i)?1'b1:1'b0;
        end
    end

endmodule


module tg(output reg [9:0]address,input [1023:0]add);
    initial begin
        $monitor($time,,,,"address=%b   add=%b",address,add);
        address=1023;
        #2 address=0;
        #2 address=1;
        #2 $finish;
    end
endmodule

module wb;
    wire [9:0]a;
    wire [1023:0]b;
    decoder d1(a,b);
    tg tg_1(a,b);
endmodule

But on running the code after compilation no o/p is seen... Help me to fix this code to implement 10:1024 bit decoder...

`assign add = 1024'b1 << address;` – Oldfart Apr 24 '18 at 17:21 — Oldfart, Apr 24 '18 at 17:21

score 3 · Answer 1 · answered Apr 24 '18 at 17:07

Since you declared i as reg [9:0]i;, the following will never be true: i == 1024. after 1023 'i' will just overflow and become '0' again.

So, your loop will never exit.

    for(i=0;i<1024;i=i+1) begin // will always be less than 1024
        add[i]=(address==i)?1'b1:1'b0;
    end

either make it as reg [10:0] or declare it as integer.

integer i; // <<< 
always@(address) begin
    for(i=0;i<1024;i=i+1) begin
        add[i]=(address==i)?1'b1:1'b0;
    end
end

10:1024 bit decoder in verilog

1 Answers1