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Questions tagged [vlsi]

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.

In addition, VLSI Technology, Inc was a company which designed and manufactured custom and semi-custom ICs. The company was based in Silicon Valley, with headquarters at 1109 McKay Drive in San Jose, California. Along with LSI Logic, VLSI Technology defined the leading edge of the application-specific integrated circuit (ASIC) business, which accelerated the push of powerful embedded systems into affordable products.

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Why delays cannot be synthesized in verilog?

I have always read that delays declared in a RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code. For example: x = #10 y; will be considered as x…
Anand
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VLSI: Registers automation

I'm looking for Registers automation solution for VLSI design. i.e, some standard way to describe RTL registers in some text file, or XML, that can be processed to Verilog, VHDL, Specman, System Verilog, C header and HTML/PDF documentation. Any…
Zvika
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AXI4 delay transactions

I am just looking for advice. I currently have a custom IP integrated in VHDL which has a AXI4 slave input and an AXI4 master output, and currently the signals are directly tied together. I would like to add a customizable latency to the AXI…
MateoConLechuga
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How can I use $display statement within sequence block, to display some info in System Verilog Assertions (SVAs)?

I want sequence blocks to display some information, while they are being executed. e.g.: sequence A; a; $display ("Signal A asserted here"); endsequence I tried this code, but encountered the following error: Task $display is invoked where…
Anand
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Integer input ports in verilog similar to vhdl?

I am a newbie to verilog. I have constructed my code using integer inputs and outputs in vhdl. Now i want to construct the same code in verilog. But I came to know that the input ports in verilog cant be of integer type. What can be done. I would…
Sai Rahul
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VHDL internal signal to change output - not working?

I have this PC module, very simple (Code at the end). I first generate some input signal port_int and at the end of the process say pc_out <= port_int. My goal is to either increment or add or subtract from PC, depending on input signals. In the…
Vidak
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Verilog: how to take the absolute value

In verilog I have an array of binary values. How do I take the absolute value of the subtracted values ? Verilog code: module aaa(clk); input clk; reg [7:0] a [1:9]; reg [7:0] s [1:9]; always@(posedge clk) begin s[1] = a[1] -…
Pravin shelton
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how to declare integer variable in verilog to keep track of a value to be used in multiple for loops?

so I have this assignment to make a generic Wallace tree multiplier in Verilog, I wrote the code but didn't test it yet. my problem is in the 2nd stage where I am supposed to bypass some wires which couldn't fit in the current stage into the next…
abdo Salm
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What is the difference between 2'b0 and 2'd0?

I was tying a port to zero in my design. What is the difference between 2'b0 and 2'd0 in Verilog? What does b and d actually mean?
Kavya
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Verilog basic gate data flow not working for NAND & NOR, but works for XNOR & XOR

I have some basic code using data flow statements, but nor and nand functions are not working with this. module basic_gates_bitwise_df( input A, input B, output andd,orr,nota,nandd,norr,xorr,xnorr ); assign andd=A&B; assign orr=A|B; assign…
vishnu lal
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Systemverilog function synthesis - automatic vs static

In the context of combinatorial logic synthesis (not simulation): When should a function be declared as automatic ? When should a function be declared as static ?
shaiko
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SRAM simulation in pspice

This is my code for SRAM simulation in pspice SRAM simulation VDD 3 0 DC 5V VWL 4 0 PWL (9us 0V 10us 5V 90us 5V 91us 0V) VBL1 5 0 PWL (0 0V 1us 5V 100us 5V 101us 0V) VBL2 6 0 PWL (0 0) M1 1 2 3 3 PMOS M2 1 2 0 0 NMOS M3 2 1 3 3 PMOS M4 2 1 0 0…
Psychofreak
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What is the diffrence between Non-Consecutive GoTo Repetition Operator and Repetition Non-Consecutive in system verilog?

I'm currently reading Ashok Mehta's system Verilog assertion textbook. Now I have encountered a doubt. I couldn't understand what is the difference between -> and = operator. I.e, Non-Consecutive GoTo Repetition Operator and Repetition…
Prasanna Shanbhogue
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How to understand the blocking and non blocking statements in verilog?

I understood the basic difference between blocking and non-blocking statements in Verilog. But still it is not possible for me to understand what's happening & when and where to use blocking and non-blocking statements. For example, consider simple…
Prasanna Shanbhogue
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Efficient Signed Multiplier with good timing

I am making a signed multiplier for that i have created half adder, full adder, ripple carry adder and then finally a multiplier. The code is shown below. How can i make it faster to achieve better timing. My final task is to make a fir…
Zohaib Ramzan
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