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Questions tagged [vlsi]

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.

In addition, VLSI Technology, Inc was a company which designed and manufactured custom and semi-custom ICs. The company was based in Silicon Valley, with headquarters at 1109 McKay Drive in San Jose, California. Along with LSI Logic, VLSI Technology defined the leading edge of the application-specific integrated circuit (ASIC) business, which accelerated the push of powerful embedded systems into affordable products.

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system verilog interface for multiple clocks

My DUT is a memory controller. I have to write a system verilog interface for the DUT. Memory Controller DUT supports 32 AXI Masters. When I am writing an AXI interface, it will consist of ACLK which is generated and passed on through the…
user3556021
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tcl text processing - rearrange values in rows and columns based on user defined value

I am new to tcl and would like to use it in text processing of a simple case. The following format is in Liberty (.lib file) which is used in chip design. I would be truly indebted for any help on this. Here is a snippet of my file (text processing…
edaloke
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k-Nearest Neighbour Algorithm in verilog

Im planning to do KNN's verilog implementation. But the problem is the euclidean distance measurement term associated with KNN,since it needs Subtraction,squaring,adding. I think,the code will become complex when i code knn with euclidean…
Viz
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Microwind does not create my equation in compile

I user microwind and try to build the mask from the compile one line choice but it wont let me the equation simplified is ~A&(~B|~C|D)
kn13
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I understand the fundamentals of verilog, but test bench just won't make sense

Half Adder: `timescale = 1ns/100ps //timescale ratio //actual HDL module half_add(a,b,sum, carry); input a,b; output sum, carry; wire sum, carry; and(sum,a,b); xor(carry,a,b); endmodule Test bench: module half_addTB; reg a,b; wire…
Sergio Alonso
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Get row or column number if an address is given as input to Memory array

I am new to VHDL programming. The project regards detecting faults in a memory array. I have obtained the faulty data and address. Now I want to get the corresponding row or column number of the particular address found in memory array. Code for…
banupriya
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Regarding "D0" drive strength cell

Why in the design we do not use or consider "D0" & "D20" drive strength cell in design? is there are any reason related to the chip aging? if yes please explain me or if you know other factors except than "chip aging" then please explain
Harshit Raghav
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Scoreboard in UVM

What do we do when we have to create a scoreboard for a certain design logic? For a memory I understand that we can compare the data written to DUT at a certain address to the data read at the same address. Suppose for a basic example of full adder…
Bunty Bhai
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XOR of variables in consecutive clock cycle

I am just learning to code in verilog. I want to XOR three variable in consecutive clock cycles. For example Z1 from 1st clock cycle ,Z2 from 2nd clock cycle and Z3 from 3rd clock cycle. How can I do that. I have written something as below always @…
elsa
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How are current generation clock frequencies achieved?

I was recently reading through the design of PLLs and was thinking about how these reference clocks are generated. We know that the reference is generated from a crystal (Generally Quartz), but the oscillations produced by these crystals top out at…
Yashas Lr
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How do I drive a signal from 2 sources in system verilog

I'm trying to write a RTL model in which I monitor independent clock sources. These clock sources can have variable frequency (range 5 to 50MHz) Let us say clk1 and clk2. I'm trying to drive a signal 'toggle' which is set '1' at every posedge of…
user3547407
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How to generate PREADY signal from slave in APB protocol?

I am designing AMBA APB slave. All signals for AMBA APB in my design are being generated properly from master side but in what case my slave should generate PREADY signal? PENABLE, PSEL, PADDR and PDATA are avalible from master. When should my slave…
Payal
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In VLSI Testing why do we perform mbist before scan insertion in DFT (Design for testability)?

In DFt (Design for testability), we can perform MBIST at any stage of DFT Flow. What is the specific advantage of doing Mbist Before scan insertion?
Shamal Madhav
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Why latch doesn't get inferred for following logic?

Why following code does not infer latch? How does tool know what to be assigned to "e" if d and rst both are "0" ? module tmp(input d, input clk, input rst, output reg o, output reg e); always@(posedge clk) …
user2624915
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wrong values at adder output in verilog module

I have written a gate level code for adder in Verilog. The output the adder is shown below. As you can see the sum and cout are always in z. I don't know why. Could you check what am I missing ? Thanks for your time. OUTPUT: a = x, b = x, cin = x,…
user_rak
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