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Questions tagged [vlsi]

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.

In addition, VLSI Technology, Inc was a company which designed and manufactured custom and semi-custom ICs. The company was based in Silicon Valley, with headquarters at 1109 McKay Drive in San Jose, California. Along with LSI Logic, VLSI Technology defined the leading edge of the application-specific integrated circuit (ASIC) business, which accelerated the push of powerful embedded systems into affordable products.

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what does Innovus dbGet command top.insts.cell.baseClass mean ? what are these values of top.insts.cell.baseClass mean?

dbGet command can be used to retrieve all the instances of the top block but exactly what are these values insts.cell.cellbaseClass? how can I change them to point certain other level of hierarchy rather than with going to the top? also what is the…
Nagendra Prasad
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"assign" followed by "always" - what is the order of evaluation?

I found the following MAC code in a verilog course and I am not able to make sense of how the MAC unit's earlier output is being fedback to the adder so that it can add this to the multiplier output. module mult_acc(input data1,data2,…
Kanmani
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Does adding buffer in a digital path increase the delay or reduce the delay and why?

I am confused as I have seen that in some cases it increases the delay and in some cases it reduces the delay
user19457634
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Verilog [dot] meaning?

What does this " .depth_log2(7) " and .i_wclk mean in Verilog code? asynch_fifo #(.depth_log2(7), .data_width(22), .rd_flop1_megedge(1'b1), ) USB2_ASYNCH_FIFO ( .i_wclk(i_usb2_sieclockin_ip), ); I'm not able to understand what that…
AWESOMENESS FOREVER
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What's the difference between `transaction and `transaction`event in VHDL

I understand that event is when the signal *transitions* to/from a value. transaction is when a signal is assigned a value, even if the value is the same as the previous value. My question is what is transactionevent? Does it mean that -both- a…
CCRCCR
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What is the Difference Between Actual and Formal Arguments in Systemverilog DPI?

In SystemVerilog design I am using DPI-C with c program functions. While running simulation on both files, I am getting error: "Actual type is not supported for DPI open array". I want to know which argument is called actual and which is called…
Gaurav Lodhi
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How can I reset my SoC from cmm script using RISC-V trace32 debugger. I don't have TRST or SRST serial lines connected to SoC

My cmm script is something like this : ..start of cmm script ""GTL config and GTL connect"" ""some JTAG.SHIFT operations"" JTAG.PIN DISable system.mode prepare ;Need a reset here. I am trying this to reset my SoC WAIT 10.MS …
Yash
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Is there an open source H.264 implementation on FPGA?

I want to design and implement an H.264 baseline/main profile encoder on FPGA for real-time HD video processing. To begin with, I am looking for design examples that would help me to understand the H.26 implementation on FPGA. Therefore, is there…
cuteolaf
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Difference between shift operation using concatenate operator {} and shift operator << in verilog

reg [3:0]a; reg in; a <= {a[2:0],in}; //1- Using Concatenate Operator a <= a<<1; //2- Using Shift operator What is the difference between 1 & 2 in terms of: a) Speed of operation. b) Hardware Implementation in…
Subham Kumar
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applying stimulus to FPGA using PC

Is there any way I can apply stimulus signals on my FPGA board from my PC itself, and view the output of hardware in any simulation software? I am working on Spartan 3A development board provided by numato labs (elbert…
Sparsh
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Scaling delay values in Design compiler topographical

I want to scale delay values in TLU plus file to zero . How can we achieve that in design compiler topographical mode. How can we scale delay values to zero of TLU plus file in DC topo
thriveni reddy 98
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Shift Register in verilog

I have designed a serial in parallel out shift register as input register for an encoder module ShiftRegister_SIPO(clk, in, out); input clk,in; output [3:0] out; reg [3:0] tmp; always @(posedge clk) begin tmp = {tmp[2:0], in}; end assign PO =…
elsa
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Does SystemVerilog Generate support delays?

I thought of generating clock using genvar like below: reg [7:0]clk; genvar i; generate for (i=0; i < 7; i++) begin #1 clk[i]=~clk[i]; end endgenerate I am getting an…
SUNODH
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Why the vivado 2017.4 is showing error here?

My code is: module circuilar_fifo; localparam B=3,W=2; input wire clk,reset,wr,rd; input wire [B-1:0] wr_data; output wire [B-1:0] rd_data; output wire full,empty; Isn't this one of the correct method of declaring input outputs? But why does the…
Prasanna Shanbhogue
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I cant compile this VHDL code because of z but i dont know why and how to fix it

Im getting this error in compiling this VHDL code with ModelSim: ** Error: testVHDL_5.vhd(14): Cannot read output "z". # VHDL 2008 allows reading outputs. # This facility is enabled by compiling with -2008. VHDL code: library IEEE; use…
Stelios Spector
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